KR960036009A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR960036009A
KR960036009A KR1019960007924A KR19960007924A KR960036009A KR 960036009 A KR960036009 A KR 960036009A KR 1019960007924 A KR1019960007924 A KR 1019960007924A KR 19960007924 A KR19960007924 A KR 19960007924A KR 960036009 A KR960036009 A KR 960036009A
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South Korea
Prior art keywords
insulating film
connection terminal
external connection
forming
semiconductor device
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KR1019960007924A
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Korean (ko)
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KR100216642B1 (en
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마사토시 아까가와
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모기 쥰이찌
신꼬오 덴기 고오교오 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 간단한 구성으로 제조가 용이하고, 저가로 제조할 수 있는 반도체장치에 관한 것이다.The present invention relates to a semiconductor device which is simple to manufacture and which can be manufactured at low cost.

본 발명은 반도체칩(23)의 비활성막(34)상에 형성된 제1절연피막(38)의 표면에 상기 반도체칩(32)의 전극(36)에 접속하여 배선패턴(40)이 형성되고, 상기 배선패턴(40)상에 배선패터너(40)의 외부접속단자접합부를 노출하여 제2 절연피막(42)이 형성되고, 상기 노출된 외부접속단자접합부에 외부접속단자(46)가 형성되어 있는 것을 특징으로 한다.The wiring pattern 40 is formed by connecting to the electrode 36 of the semiconductor chip 32 on the surface of the first insulating coating 38 formed on the passive film 34 of the semiconductor chip 23, The second insulating film 42 is formed by exposing the junction of the external connection terminal of the wiring patterner 40 on the wiring pattern 40 and the external connection terminal 46 is formed on the exposed external connection terminal junction .

Description

반도체장치 및 그 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 반도체장치의 제1 실시형태를 나타낸 단면도.1 is a cross-sectional view showing a first embodiment of a semiconductor device;

Claims (9)

비활성화막이 형성된 반도체칩면상에 상기 반도체칩의 전극을 노출하여 제1절연피막이 형성되고, 상기 제1절연피막의 표면에 상기 반도체칩의 전극에 접속하여 배선패턴이 형성되고, 상기 배선패턴상에 배선패턴의 외부접속단자접합부를 노출하여 제2 절연피막이 형성되고, 상기 노출한 외부접속단자접합부에 외부접속단자가 형성되어 있는 것을 특징으로 하는 반도체장치.The first insulating film is formed by exposing the electrode of the semiconductor chip on the surface of the semiconductor chip on which the inactivating film is formed, the wiring pattern is formed on the surface of the first insulating film by connecting to the electrode of the semiconductor chip, Wherein the second insulating film is formed by exposing the external connection terminal portion of the pattern and the external connection terminal is formed at the exposed external connection terminal portion. 제1항에 있어서, 상기 제1절연피막이 감광성폴리이미드막으로 형성되어 있는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the first insulating film is formed of a photosensitive polyimide film. 제1항 또는 제2항에 있어서, 상기 제2 절연피막이 감광성솔더레지스트막으로 형성되어 있는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1 or 2, wherein the second insulating film is formed of a photosensitive solder resist film. 제1항 내지 제3항 중 어느 한항에 있어서, 상기 외부접속단자 범프인 것을 특징으로 하는 반도체장치.The semiconductor device according to any one of claims 1 to 3, wherein the external connection terminal bump is the external connection terminal bump. 제1항 내지 제4항 중 어느 한항에 있어서, 상기 반도체칩을 복수개 구비하고, 상기 복수의 반도체칩상에 공통의 상기 제1 절연피막이 형성되고, 상기 복수의 반도체칩의 소요의 전극끼리 상기 배선패턴에 의해 접속되고, 상기 배선패턴상에 공통의 상기 제2 절연피막이 형성되어 있는 것을 특징으로 하는 반도체장치.The semiconductor device according to any one of claims 1 to 4, wherein a plurality of the semiconductor chips are provided, the first insulating film common to the plurality of semiconductor chips is formed, And the common second insulating film is formed on the wiring pattern. 제1항 내지 제5항 중 어느 한항에 있어서, 상기 제2 절연피막에 형성된 투공의 저면에 노출된 외부 접속단자접합부에 상기 투공의 저면, 내벽면 및 주연부를 피복하는 랜드가 형성되고, 상기 랜드에 상기 외부접속단자가 접속되어 있는 것을 특징으로 하는 반도체장치.6. The semiconductor device according to any one of claims 1 to 5, wherein a land covering the bottom surface, the inner wall surface and the peripheral portion of the through hole is formed in the external connection terminal joint portion exposed on the bottom surface of the through hole formed in the second insulation film, And the external connection terminal is connected to the external connection terminal. 전극을 노출하여 비활성화막이 형성된 반도체칩면상에 감광성레지스트를 도포하고, 상기 감광성레지스트에 노광, 현상을 행하고, 상기 전극을 노출하는 투공을 형성하여 제1 절연피막으로 한후, 상기 투공을 포함하는 상기 제1 절연피막의 표면에 스퍼터링 등에 의해 도체층을 피착형성하고, 상기 도체층에 에칭을 행하여 상기 투공부분에서 상기 전극과 전기적으로 도통하는 배선패턴을 형성하고, 이어서, 상기 배선패턴을 포함하는 상기 제1 절연피막의 표면에 감광성레지스트를 도포하고, 상기 감광성레지스트에 노광, 현상을 행하여 상기 배선패턴상에서 노출하는 투공을 형성하여 제2 절연피막으로 하고, 상기 제2절연피막의 투공위치에 땜납 볼 등의 외부접속단자를 접속하는 것을 특징으로 하는 반도체장치의 제조방법.A step of applying a photosensitive resist on a surface of a semiconductor chip on which a passivation film is formed by exposing an electrode, performing exposure and development on the photosensitive resist, forming a through hole exposing the electrode to form a first insulating film, 1 A conductive layer is formed on the surface of an insulating coating by sputtering or the like and etching is performed on the conductive layer to form a wiring pattern electrically conducting with the electrode in the conductive pattern, Forming a second insulating film on the surface of the first insulating film by applying a photosensitive resist to the first insulating film and exposing and developing the photosensitive resist to form a through hole exposed on the wiring pattern to form a solder ball Or the like is connected to the external connection terminal. 제7항에 있어서, 상기 제2 절연피막의 표면에 도체층을 형성하고, 상기 도체층에 에칭을 행하고 상기 제2 절연피막에 형성된 투공부분에 있어서, 상기 제1 절연피막의 표면에 형성한 배선패턴과 전기적으로 도통하는 배선패턴을 형성한 후, 제2 절연피막의 표면에 감광성레지스트를 도포하고 그 위에 상층의 절연피막을 형성함으로서, 배선패턴을 다층형성하는 것을 특징으로 하는 반도체장치의 제조방법.8. The method of manufacturing a semiconductor device according to claim 7, wherein a conductor layer is formed on the surface of the second insulating coating, etching is performed on the conductor layer, and in a penetrating agent formed on the second insulating coating, Forming a wiring pattern which is electrically conductive with the wiring pattern, applying a photosensitive resist to the surface of the second insulating coating, and forming an insulating film of an upper layer on the surface of the second insulating coating, Way. 제7항 또는 제8항에 있어서, 상기 비활성화막상에 반도체칩의 전극부분을 제외하고, 상기 절연피막을 형성할때의 포토리소그래피공정에서 사용하는 자외선으로부터 반도체칩의 회로를 보호하는 자외선차폐층을 설비한 후, 소요의 절연피막의 형성가공을 행하는 것을 특지으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 7 or 8, further comprising the steps of: forming an ultraviolet shielding layer for protecting the circuit of the semiconductor chip from ultraviolet rays used in a photolithography process in forming the insulating film, And a step of forming a necessary insulating film after the step of forming the insulating film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960007924A 1995-03-24 1996-03-22 Semiconductor device and method of manufacture of the same KR100216642B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP95-065607 1995-03-24
JP6560795 1995-03-24
JP25986195A JP3356921B2 (en) 1995-03-24 1995-10-06 Semiconductor device and method of manufacturing the same
JP95-259861 1995-10-06

Publications (2)

Publication Number Publication Date
KR960036009A true KR960036009A (en) 1996-10-28
KR100216642B1 KR100216642B1 (en) 1999-09-01

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JP4024958B2 (en) 1999-03-15 2007-12-19 株式会社ルネサステクノロジ Semiconductor device and semiconductor mounting structure
JP3450238B2 (en) 1999-11-04 2003-09-22 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
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JP2001308092A (en) * 2000-04-18 2001-11-02 Toyo Kohan Co Ltd Multilayered metal plate used for forming interconnection on semiconductor wafer, and method for forming the interconnection on semiconductor wafer
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JP3879816B2 (en) 2000-06-02 2007-02-14 セイコーエプソン株式会社 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, LAMINATED SEMICONDUCTOR DEVICE, CIRCUIT BOARD AND ELECTRONIC DEVICE
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US9704769B2 (en) 2014-02-27 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)

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Publication number Publication date
KR100216642B1 (en) 1999-09-01
JPH08330313A (en) 1996-12-13
JP3356921B2 (en) 2002-12-16

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