KR960036009A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- KR960036009A KR960036009A KR1019960007924A KR19960007924A KR960036009A KR 960036009 A KR960036009 A KR 960036009A KR 1019960007924 A KR1019960007924 A KR 1019960007924A KR 19960007924 A KR19960007924 A KR 19960007924A KR 960036009 A KR960036009 A KR 960036009A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- connection terminal
- external connection
- forming
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 간단한 구성으로 제조가 용이하고, 저가로 제조할 수 있는 반도체장치에 관한 것이다.The present invention relates to a semiconductor device which is simple to manufacture and which can be manufactured at low cost.
본 발명은 반도체칩(23)의 비활성막(34)상에 형성된 제1절연피막(38)의 표면에 상기 반도체칩(32)의 전극(36)에 접속하여 배선패턴(40)이 형성되고, 상기 배선패턴(40)상에 배선패터너(40)의 외부접속단자접합부를 노출하여 제2 절연피막(42)이 형성되고, 상기 노출된 외부접속단자접합부에 외부접속단자(46)가 형성되어 있는 것을 특징으로 한다.The wiring pattern 40 is formed by connecting to the electrode 36 of the semiconductor chip 32 on the surface of the first insulating coating 38 formed on the passive film 34 of the semiconductor chip 23, The second insulating film 42 is formed by exposing the junction of the external connection terminal of the wiring patterner 40 on the wiring pattern 40 and the external connection terminal 46 is formed on the exposed external connection terminal junction .
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제1도는 반도체장치의 제1 실시형태를 나타낸 단면도.1 is a cross-sectional view showing a first embodiment of a semiconductor device;
Claims (9)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP95-065607 | 1995-03-24 | ||
JP6560795 | 1995-03-24 | ||
JP25986195A JP3356921B2 (en) | 1995-03-24 | 1995-10-06 | Semiconductor device and method of manufacturing the same |
JP95-259861 | 1995-10-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960036009A true KR960036009A (en) | 1996-10-28 |
KR100216642B1 KR100216642B1 (en) | 1999-09-01 |
Family
ID=26406746
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960007924A KR100216642B1 (en) | 1995-03-24 | 1996-03-22 | Semiconductor device and method of manufacture of the same |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP3356921B2 (en) |
KR (1) | KR100216642B1 (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW448524B (en) | 1997-01-17 | 2001-08-01 | Seiko Epson Corp | Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment |
WO1998040915A1 (en) | 1997-03-10 | 1998-09-17 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board |
JP3335575B2 (en) * | 1997-06-06 | 2002-10-21 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
JP3068534B2 (en) * | 1997-10-14 | 2000-07-24 | 九州日本電気株式会社 | Semiconductor device |
US6441487B2 (en) * | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
KR100449307B1 (en) * | 1998-06-12 | 2004-09-18 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and method for manufacturing the same |
US6903451B1 (en) | 1998-08-28 | 2005-06-07 | Samsung Electronics Co., Ltd. | Chip scale packages manufactured at wafer level |
WO2000044043A1 (en) * | 1999-01-22 | 2000-07-27 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
KR100526061B1 (en) * | 1999-03-10 | 2005-11-08 | 삼성전자주식회사 | Method for manufacturing chip scale package at wafer level |
JP4024958B2 (en) | 1999-03-15 | 2007-12-19 | 株式会社ルネサステクノロジ | Semiconductor device and semiconductor mounting structure |
JP3450238B2 (en) | 1999-11-04 | 2003-09-22 | Necエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP2001196381A (en) * | 2000-01-12 | 2001-07-19 | Toyo Kohan Co Ltd | Semiconductor device, metallic laminated board used for formation of circuit on semiconductor, and method for forming circuit |
CN100336426C (en) | 2000-02-25 | 2007-09-05 | 揖斐电株式会社 | Multilayer printed wiring board and method ofr producing multilayer printed wiring board |
JP2001308092A (en) * | 2000-04-18 | 2001-11-02 | Toyo Kohan Co Ltd | Multilayered metal plate used for forming interconnection on semiconductor wafer, and method for forming the interconnection on semiconductor wafer |
JP2001308095A (en) | 2000-04-19 | 2001-11-02 | Toyo Kohan Co Ltd | Semiconductor device and method of manufacture |
JP3879816B2 (en) | 2000-06-02 | 2007-02-14 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, LAMINATED SEMICONDUCTOR DEVICE, CIRCUIT BOARD AND ELECTRONIC DEVICE |
JP2002094082A (en) | 2000-07-11 | 2002-03-29 | Seiko Epson Corp | Optical element and its manufacturing method and electronic equipment |
KR100797422B1 (en) | 2000-09-25 | 2008-01-23 | 이비덴 가부시키가이샤 | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
JP3939504B2 (en) * | 2001-04-17 | 2007-07-04 | カシオ計算機株式会社 | Semiconductor device, method for manufacturing the same, and mounting structure |
JP4217639B2 (en) | 2004-02-26 | 2009-02-04 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
JP4238843B2 (en) | 2005-06-21 | 2009-03-18 | セイコーエプソン株式会社 | Semiconductor chip, semiconductor chip manufacturing method, and electronic device |
JP4265575B2 (en) | 2005-06-21 | 2009-05-20 | セイコーエプソン株式会社 | Semiconductor chip and electronic equipment |
JP5272331B2 (en) * | 2007-05-23 | 2013-08-28 | 株式会社デンソー | Semiconductor device |
JP4607152B2 (en) * | 2007-07-09 | 2011-01-05 | Okiセミコンダクタ株式会社 | Semiconductor device |
US9704769B2 (en) | 2014-02-27 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP) |
-
1995
- 1995-10-06 JP JP25986195A patent/JP3356921B2/en not_active Expired - Fee Related
-
1996
- 1996-03-22 KR KR1019960007924A patent/KR100216642B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100216642B1 (en) | 1999-09-01 |
JPH08330313A (en) | 1996-12-13 |
JP3356921B2 (en) | 2002-12-16 |
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