KR100216642B1 - Semiconductor device and method of manufacture of the same - Google Patents
Semiconductor device and method of manufacture of the same Download PDFInfo
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- KR100216642B1 KR100216642B1 KR1019960007924A KR19960007924A KR100216642B1 KR 100216642 B1 KR100216642 B1 KR 100216642B1 KR 1019960007924 A KR1019960007924 A KR 1019960007924A KR 19960007924 A KR19960007924 A KR 19960007924A KR 100216642 B1 KR100216642 B1 KR 100216642B1
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/151—Die mounting substrate
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Abstract
본 발명은 간단한 구성으로 제조가 용이하고, 저가로 제조할 수 있는 반도체장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is easy to manufacture with a simple configuration and can be manufactured at low cost.
본 발명은 반도체칩(32)의 비활성화막(34)상에 형성된 제1 절연피막(38)의 표면에 상기 반도체칩(32)의 전극(36)에 접속하여 배선패턴(40)이 형성되고, 상기 배선패턴(40)상에 배선패턴(40)의 외부접속단자접합부를 노출하여 제2 절연피막(42)이 형성되고, 상기 노출된 외부접속단자접합부에 외부접속단자(46)가 형성되어 있는 것을 특징으로 한다.In the present invention, the wiring pattern 40 is formed on the surface of the first insulating film 38 formed on the passivation film 34 of the semiconductor chip 32 by connecting to the electrode 36 of the semiconductor chip 32. The second insulating film 42 is formed on the wiring pattern 40 by exposing the external connection terminal junction of the wiring pattern 40, and the external connection terminal 46 is formed on the exposed external connection terminal junction. It is characterized by.
Description
제1도는 반도체장치의 제1 실시형태를 나타낸 단면도.1 is a cross-sectional view showing a first embodiment of a semiconductor device.
제2도는 반도체장치의 제조공정도.2 is a manufacturing process diagram of a semiconductor device.
제3도는 반도체장치의 제2실시형태를 나타낸 단면도.3 is a cross-sectional view showing a second embodiment of the semiconductor device.
제4도는 범프 접합부에 랜드를 형성한 반도체장치의 실시형태를 나타낸 단면도.4 is a cross-sectional view showing an embodiment of a semiconductor device in which lands are formed at bump junctions.
제5도는 배선패턴을 다층 형성한 반도체장치의 실시형태를 나타낸 단면도.5 is a cross-sectional view showing an embodiment of a semiconductor device in which a wiring pattern is formed in multiple layers.
제6도는 회로용 소자를 조립한 반도체장치의 실시형태를 나타낸 단면도.6 is a cross-sectional view showing an embodiment of a semiconductor device incorporating a circuit element.
제7도는 감광성 레지스트를 노광하는 모양을 나타낸 단면도.7 is a cross-sectional view showing a state of exposing a photosensitive resist.
제8도는 비활성화막상에 자외선 차폐층을 설비한 단면도.8 is a cross-sectional view of providing an ultraviolet shielding layer on a passivation film.
제9도는 제1 절연피막을 형성할 때의 노광의 모양을 나타낸 단면도.9 is a cross-sectional view showing the state of exposure when the first insulating film is formed.
제10도는 자외선 차폐층을 설비한 반도체장치의 실시형태를 나타낸 단면도.10 is a cross-sectional view showing an embodiment of a semiconductor device equipped with an ultraviolet shielding layer.
제11도는 종래의 반도체장치의 일례를 나타낸 단면도.11 is a cross-sectional view showing an example of a conventional semiconductor device.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
30 : 반도체장치 32 : 반도체칩30: semiconductor device 32: semiconductor chip
34 : 비활성화막 36 : Al 패드34: passivation film 36: Al pad
38 : 제1 절연피막 40, 40b, 40c : 배선패턴38: first insulating film 40, 40b, 40c: wiring pattern
40a : 외부접속단자 접합부 42 : 제2 절연피막40a: External connection terminal junction 42: Second insulating film
44 : 투공 48 : 보호막44: Perforation 48: Shield
50 : 랜드 52 : 제3 절연피막50 land 52: third insulating film
54 : 제4 절연피막 56 : 콘덴서54: fourth insulating film 56: capacitor
58 : 저항 60 : 자외선 차폐층58: resistance 60: ultraviolet shielding layer
본 발명은 칩사이즈의 반도체장치에 관한 것이다.The present invention relates to a chip size semiconductor device.
반도체칩이 탑재된 반도체장치는 그 실장밀도를 높이기 위해서 소형화에 대한 요청이 강하게 요구되고 있다.In order to increase the mounting density of a semiconductor device equipped with a semiconductor chip, a request for miniaturization is strongly demanded.
이러한 반도체장치의 소형화는 반도체 칩을 봉입하는 패키지의 소형화로 바로 이어진다.The miniaturization of such a semiconductor device leads directly to the miniaturization of a package encapsulating a semiconductor chip.
이러한 요청을 만족시키기 위해서, 최근에 CSP타입, 즉 칩사이즈 패키지가 출현하고 있다.In order to satisfy such a request, a CSP type, that is, a chip size package has recently emerged.
CSP 타입에는 여러 종류가 있지만, 제11도에 그 일례를 나타낸다.There are various types of CSP types, but an example thereof is shown in FIG.
10은 반도체칩, 12는 세라믹기판이다. 세라믹기판(12)은 반도체칩(10)과 거의 같은 사이즈로 형성되어 있다. 세라믹기판(12)상에는 배선패턴(14)이 형성되고, 상기 배선패턴(14)은 비아(16)를 거쳐서 세라믹기판(12) 하면측에 소요 배치로 형성된 랜드(외부단자)(18)에 접속되어 있다.10 is a semiconductor chip and 12 is a ceramic substrate. The ceramic substrate 12 is formed in substantially the same size as the semiconductor chip 10. A wiring pattern 14 is formed on the ceramic substrate 12, and the wiring pattern 14 is connected to a land (external terminal) 18 formed in a required arrangement on the lower surface side of the ceramic substrate 12 via a via 16. It is.
반도체칩(10)은 Au 범프(20)와 AgPd 페이스트(22)를 거쳐서 배선패턴(14)에 접속되고, 반도체칩 (10)과 세라믹기판(12) 사이의 빈틈에는 수지(24)가 봉지된다.The semiconductor chip 10 is connected to the wiring pattern 14 through the Au bumps 20 and the AgPd paste 22, and the resin 24 is sealed in the gap between the semiconductor chip 10 and the ceramic substrate 12. .
상기 반도체장치에 의하면 소형화는 달성되지만, 세라믹기판(12)을 사용하거나, Au 범프(20)를 사용하고 있기 때문에 고가로 된다.According to the semiconductor device, miniaturization is achieved, but it is expensive because the ceramic substrate 12 or the Au bumps 20 are used.
그래서, 본 발명은 상기한 문제점을 해결하기 위해서 행해진 것으로서, 그 목적으로 하는 바는 간단한 구성으로 제조가 용이하고 저가로 제조할 수 있는 반도체장치를 제공하는 것에 있다.Therefore, the present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor device which can be manufactured easily and at low cost with a simple configuration.
본 발명은 상기 목적을 달성하기 위해서 다음과 같은 구성을 구비한다.The present invention has the following configuration to achieve the above object.
즉, 비활성화막이 형성된 반도체칩 면상에 상기 반도체칩의 전극을 노출하여 제1 절연피막이 형성되고, 상기 제1 절연피막의 표면에 상기 반도체칩의 전극에 접속하여 배선패턴이 형성되고, 상기 배선패턴상에 배선패턴의 외부접속단자 접합부를 노출하여 제2 절연피막이 형성되고, 상기 노출된 외부접속단자 접합부에 외부접속단자가 형성되어 있는 것을 특징으로 한다.That is, a first insulating film is formed by exposing the electrode of the semiconductor chip on the surface of the semiconductor chip on which the passivation film is formed, and a wiring pattern is formed on the surface of the first insulating film by connecting to the electrode of the semiconductor chip. The second insulating film is formed by exposing the external connection terminal junction of the wiring pattern, and the external connection terminal is formed in the exposed external connection terminal junction.
또, 상기 제1 절연피막이 감광성 폴리이미드막으로 형성된 것을 특징으로 한다.The first insulating film is formed of a photosensitive polyimide film.
또, 상기 제2 절인피막이 감광성 솔더레지스트막으로 형성된 것을 특징으로 한다.In addition, the second pickled coating is formed of a photosensitive solder resist film.
또, 상기 외부접속단자가 범프인 것을 특징으로 한다.In addition, the external connection terminal is characterized in that the bump.
또, 상기 반도체 칩을 복수개 구비하고, 상기 복수의 반도체칩상에 공통의 상기 제1 절연피막이 형성되고, 상기 복수의 반도체칩의 소요의 전극끼리가 상기 배선패턴에 의해 접속되고, 상기 배선패턴상에 공통의 상기 제2 절연피막이 형성되어 있는 것을 특징으로 한다.Further, a plurality of the semiconductor chips are provided, a common first insulating film is formed on the plurality of semiconductor chips, electrodes required by the plurality of semiconductor chips are connected by the wiring pattern, and on the wiring pattern. The said common 2nd insulating film is formed, It is characterized by the above-mentioned.
또,상기 제2절연피막에 형성된 투공의 저면에 노출된 외부 접속단자 접합부에 상기 투공의 저면, 내벽면 및 가장자리 부를 피복하는 랜드가 형성되고, 상기 랜드에 상기 외부접속단자가 접속되어 있는 것을 특징으로 한다.Further, a land covering the bottom surface, the inner wall surface, and the edge portion of the perforation is formed in the junction portion of the external connection terminal exposed on the bottom surface of the perforation formed in the second insulating film, and the external connection terminal is connected to the land. It is done.
또, 반도체장치의 제조방법에 있어서, 전극을 노출하여 비활성화막이 형성된 반도체칩면상에 감광성 레지스트를 도포하고,상기 감광성 레지스트에 노광, 현상을 행하고, 상기 전극을 노출시키는 투공을 형성하여 제1 절연피막으로 한 후 상기 투공을 포함하는 상기 제1 절연피막의 표면에 스퍼터링 등에 의해 도체층을 피착형성하고, 상기 도체층에 에칭을 행하여 상기 투공부분으로 상기 전극과 전기적으로 도통하는 배선패턴을 형성하고, 이어서 상기 배선패턴을 포함하는 상기 제1 절연피막의 표면에 감광성 레지스트를 도포하여 상기 감광성 레지스트에 노광, 현상을 행하고, 상기 배선패턴상으로 노출하는 투공을 형성하여 제2 절연피막으로 하고, 상기 제2절연피막의 투공위치에 땜납 볼 등의 외부접속단자를 접속하는 것을 특징으로 한다.In the method of manufacturing a semiconductor device, a photosensitive resist is coated on a surface of a semiconductor chip on which an inert film is formed by exposing an electrode, the photosensitive resist is exposed and developed, and a perforation for exposing the electrode is formed to form a first insulating film. And depositing a conductor layer on the surface of the first insulating film including the through hole by sputtering or the like, and etching the conductor layer to form a wiring pattern electrically connected to the electrode through the through part. Next, a photosensitive resist is coated on the surface of the first insulating film including the wiring pattern to perform exposure and development on the photosensitive resist, thereby forming a through hole exposed on the wiring pattern to form a second insulating film. An external connection terminal such as a solder ball is connected to a pore position of the second insulating film.
또, 상기 제2절연피막의 표면에 도체층을 형성하고 상기 도체층에 에칭을 행하여 상기 제2 절연피막에 형성한 투공부분에서, 상기 제1 절연피막의 표면에 형성한 배선패턴과 전기적으로 도통하는 배선패턴을 형성한 후, 제2 절연피막의 표면에 감광성 레지스트를 도포하고, 상층의 절연피막을 형성함으로써, 배선패턴을 다층 형성하는 것을 특징으로 한다.In addition, a conductive layer is formed on the surface of the second insulating film, and the conductive layer is etched to form the second insulating film, and electrically connected to the wiring pattern formed on the surface of the first insulating film. After forming the conductive wiring pattern, a photosensitive resist is applied to the surface of the second insulating film, and the upper insulating film is formed, thereby forming a wiring pattern in multiple layers.
또, 상기 비활성화막상에 반도체칩의 전극부분을 제외하고, 상기 절연피막을 형성할 때에 포토리소그래피 공정에서 사용하는 자외선으로부터 반도체칩의 회로를 보호하는 자외선 차폐층을 설비한 후 소요의 절연피막의 형성가공을 행한 것을 특징으로 한다.When forming the insulating film, except for the electrode portion of the semiconductor chip on the passivation film, the required insulating film is formed after the ultraviolet shielding layer is provided to protect the circuit of the semiconductor chip from the ultraviolet light used in the photolithography step. It is characterized by processing.
본 발명에 의한 반도체장치에 의하면, 인터포저(interposer)로 된 제1 및 제2 절연피막을 얇게 형성할 수 있기 때문에, 얇은 반도체장치로 형성할 수 있고. 비용의 절감화도 도모할 수 있다.According to the semiconductor device according to the present invention, since the first and second insulating films made of interposers can be formed thinly, they can be formed into thin semiconductor devices. Cost reduction can also be achieved.
제1, 제2 절연피막은 경도가 그렇게 높지 않으므로, 반도체칩 표면을 보호하거나, 반도체칩과 실장기판의 사이에 생기는 열적 또는 기계적 응력을 완화하는 완충층으로서도 기능하는 효과를 거둘 수 있다.Since the hardness of the first and second insulating films is not so high, the first and second insulating films can have an effect of protecting the surface of the semiconductor chip or functioning as a buffer layer to alleviate thermal or mechanical stress generated between the semiconductor chip and the mounting substrate.
또 복수의 반도체칩의 소요의 전극끼리를 전기적으로 접속함으로써 신호의 지연방지 등의 전기적 특성의 향상을 도모하고, 또 제1 및 제2 절연피막을 공통으로 형성함으로써 제조도 용이한 효과를 거둘 수 있다.In addition, by electrically connecting the required electrodes of a plurality of semiconductor chips, it is possible to improve the electrical characteristics such as the prevention of signal delay, and to form the first and second insulating films in common, so that the manufacturing can be easily performed. have.
또, 본 발명에 의한 반도체장치의 제조방법에 의하면, 칩사이즈의 반도체장치를 용이하게 얻을 수 있어, 자외선 차폐층을 설비한 경우에는 네거티브힝의 반도체장치의 제조에 특히 유효하다.In addition, according to the method for manufacturing a semiconductor device according to the present invention, a chip size semiconductor device can be easily obtained, and when the ultraviolet shielding layer is provided, it is particularly effective for the manufacture of a negative device.
이하, 본 발명이 바람직한 실시형태를 첨부 도면에 따라서 상세히 설명하겠다.EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described in detail according to an accompanying drawing.
제1도는 반도체장치(30)의 단면도를 나타낸다.1 shows a cross-sectional view of the semiconductor device 30.
32는 반도체칩, 34는 SiO2등으로 된 비활성화막, 36은 반도체칩(32)에 제조해 넣은 전극인 Al 패드이다. Al 패드(36) 부위에는 비활성화막(34)이 형성되어 있지 않고, Al 패드(36)가 노출되어 있다. Al 패드(36)는 소요의 패턴으로 반도체칩(32)상에 다수 형성되어 있다.32 is a semiconductor chip, 34 is an inert film made of SiO 2 , and 36 is an Al pad which is an electrode manufactured in the semiconductor chip 32. The passivation film 34 is not formed in the Al pad 36, and the Al pad 36 is exposed. A large number of Al pads 36 are formed on the semiconductor chip 32 in a required pattern.
38은 제1 절연피막이고, 비활성화막(34)을 덮어 형성되어 있다. 이 제1 절연피막(38)은 감광성 폴리이미드 등의 감광성 레지스트를 사용하여 형성할 수 있다. 또, 경우에 따라서는 반도체칩 (32)에 비활성화막을 설비하지 않고, 제1 절연피막(38)이 비활성화막의 기능을 겸하게 하여도 좋다.38 is a first insulating film and is formed to cover the passivation film 34. This first insulating film 38 can be formed using photosensitive resists such as photosensitive polyimide. In some cases, the first insulating film 38 may also function as the passivation film without providing the passivation film on the semiconductor chip 32.
40은 배선패턴이고, Al 패드(36)와 전기적으로 접속되고, 소요의 패턴으로 제1 절연피막(38)상에 형성되어 있다.40 is a wiring pattern, is electrically connected to the Al pad 36, and is formed on the first insulating film 38 in a required pattern.
배선패턴(40)은, 스퍼티링 (sputtering)에 의해 Cu 또는 Al 피막을 제1 절연피막(38) 및 Al 패드(36)상에 형성하고, 이 Cu 또는 Al 피막을 에칭하여 소요 패턴으로 형성한다. 또 동박 등의 금속박을 점착하고 에칭하여 패턴을 형성하여도 좋다.The wiring pattern 40 is formed on the first insulating film 38 and the Al pad 36 by sputtering, and the Cu or Al film is etched to form a required pattern. do. Moreover, you may stick and etch metal foil, such as copper foil, and form a pattern.
42는 제2 절연피막이고, 제1 절연피막(38) 및 배선패턴(40)을 덮어 형성되어 있다.42 is a second insulating film, and is formed to cover the first insulating film 38 and the wiring pattern 40.
제2 절연피막(42)은 보호막이고, 폴리이미드 등의 여러가지 재질의 감광성 솔더레지스트를 사용할 수 있다.The second insulating film 42 is a protective film, and photosensitive solder resists of various materials such as polyimide can be used.
제2 절연피막(42)의 각 배선패턴(40)에 대응하는 적당 부위에는, 예컨대 제2 절연피막(42)상에 투공(44)이 매트릭스상의 배치가 되도록 형성되어 있다(투공(44)으로부터 노출되는 배선패턴 (40)의 부분이 외부접속단자 접합부(40a)임).A suitable portion corresponding to each wiring pattern 40 of the second insulating film 42 is formed on the second insulating film 42 so that the perforations 44 are arranged in a matrix form (from the perforations 44). The exposed portion of the wiring pattern 40 is the external connection terminal junction portion 40a).
46은 외부접속단자인 범프이고, 각 투공(44)을 통하여 각 외부접속단자 접합부(40a)에 전기적으로 접속하여 배치되고, 제2 절연피막(42)상에 돌출하여 외부접속단자에 형성되어 있다.46 is a bump which is an external connection terminal, is electrically connected to each external connection terminal junction portion 40a through each of the perforations 44, and is formed on the external connection terminal by protruding on the second insulating film 42. .
범프(46)는 도시한 바와 같이 볼범프로 형성할 수 있지만, 평탄한 랜드상, 기타 형상으로도 형성할 수도 있다. 또 범프상으로 형성하는 대신에 리드 핀을 접합하여 외부접속단자로 할 수도 있다.The bumps 46 may be formed of ball bumps as shown, but may also be formed on flat lands or other shapes. Instead of forming bumps, lead pins may be joined to serve as external connection terminals.
48은 보호막으로, 반도체칩(32), 비활성화막(34), 제1 절연피막(38)의 측벽을 덮어 형성하고, 각 층의 경계에서의 습기의 진입등을 방지한다. 보호막(48)은 제1 절연피막(38)과 같은 재질의 것을 사용하고, 제1 절연피막(38)을 형성할 때 동시에 형성하도록 하면 좋다. 또, 보호막(48)은 반드시 설비하지 않더라도 좋다. 또 보호막 대신에 금속 등으로 된 프레임를 고착하더라도 좋다.48 is a protective film, which covers the sidewalls of the semiconductor chip 32, the passivation film 34, and the first insulating film 38, and prevents moisture from entering at the boundary of each layer. The protective film 48 may be formed of the same material as the first insulating film 38 and formed simultaneously with the formation of the first insulating film 38. In addition, the protective film 48 may not necessarily be provided. Instead of the protective film, a frame made of metal or the like may be fixed.
본 실시형태의 반도체장치는 상기한 바와 같이 형성되어 있기 때문에, 반도체칩(32)과 같은 사이즈의 반도체장치 (30)로 형성할 수 있다.Since the semiconductor device of the present embodiment is formed as described above, it can be formed of a semiconductor device 30 having the same size as the semiconductor chip 32.
또 인터포저로 된 제1 및 제2 절연피막(38, 42)은 얇게 형성할 수 있기 때문에, 얇은 반도체장치(30)로 형성할 수 있다.In addition, since the first and second insulating films 38 and 42 made of interposers can be formed thinly, they can be formed by a thin semiconductor device 30.
제1 및 제2 절연피막(38, 42)은 경도가 그렇게 높지 않기 때문에 반도체칩 (32) 표면을 보호하거나, 반도체칩과 실장기판의 사이에 생기는 응력을 완화하는 완충층으로서도 기능한다.Since the hardness of the first and second insulating films 38 and 42 is not so high, the first and second insulating films 38 and 42 also function as buffer layers for protecting the surface of the semiconductor chip 32 or for relieving stress generated between the semiconductor chip and the mounting substrate.
또, 반도체칩(32)의 전극이 형성된 면과 반대측의 면은 노출시켜 방열성을 높이도록 하면 좋다. 또 방열성을 향상시키기 위해서 히트싱크 또는 히트스프레더(heat spreader)를 고착하더라도 좋다.The surface opposite to the surface on which the electrode of the semiconductor chip 32 is formed may be exposed to increase heat dissipation. In order to improve heat dissipation, a heat sink or heat spreader may be fixed.
제2도는 상기 반도체장치(30)의 제조공정의 일례를 나타낸 것이다.2 shows an example of the manufacturing process of the semiconductor device 30.
우선 반도체칩(32)이 다수개 제조되어 넣어진 웨이퍼(도시하지 않음) 표면상에 제1 절연피막(38)을 형성하기 위한 감광성 레지스트(감광성 폴리이미드)를 도포한다.First, a photosensitive resist (photosensitive polyimide) for forming the first insulating film 38 is applied onto the surface of a wafer (not shown) in which a plurality of semiconductor chips 32 are manufactured.
이어서, 감광성 레지스트의 가소를 함과 동시에, Al 패드(36) 부분의 감광성 레지스트를 제거하기 위해서 공지의 포토리소그래피 공정에 의해서 노광, 현상을 행하고, 소성하여 제1절연피막 (38)을 형성한다.Subsequently, in order to plasticize the photosensitive resist and to remove the photosensitive resist of the Al pad 36 portion, exposure and development are performed by a known photolithography process, followed by baking to form the first insulating film 38.
다음에 동 스퍼터링을 행하여, 제1 절연피막(38) 및 Al 패드(36)상에 동피막을 형성한다(동피막은 배선패턴을 형성하기 위한 도체층으로서 설비하는 것으로, 알루미늄피막 등을 형성해도 좋다). 동피막상에 더 동도금을 행함으로써 도통을 양호하게 할 수 있다. 또 동피막은 증착 등 기타 방법에 의해서 형성해도 좋다.Next, copper sputtering is performed to form a copper film on the first insulating film 38 and the Al pad 36. (The copper film is provided as a conductor layer for forming a wiring pattern. good). The conduction can be improved by further copper plating on the copper film. The copper film may be formed by other methods such as vapor deposition.
동피막상에 감광성 레지스트를 도포하고 노광, 현상, 소성하여 레지스트패턴을 형성하고, 이 레지스트패턴을 마스크로 에칭하여 배선패턴(40)을 형성한다. 그 후에 레지스트패턴을 박리한다.A photosensitive resist is coated on the copper film, exposed, developed and baked to form a resist pattern, and the resist pattern is etched with a mask to form a wiring pattern 40. Thereafter, the resist pattern is peeled off.
다음에 제2 절연피막(42)을 형성 할 제1 절연피막(38) 및 배선패턴(40)상에 감광성 레지스트(감광성 솔더레지스트)를 도포하고 노광, 현상하여 투공(44)을 형성한다.Next, a photosensitive resist (photosensitive solder resist) is applied, exposed and developed on the first insulating film 38 and the wiring pattern 40 on which the second insulating film 42 is to be formed, thereby forming a hole 44.
이 투공(44)내에 땜납 볼(범프(46))을 배치하고, 리플로하여 땜납 볼을 배선패턴(40)상에 고정한다. 또, 범프는 Ni도금, Au도금을 행하여, Ni-Au 범프를 형성하여 설비하더라도 좋다.Solder balls (bumps 46) are disposed in the through holes 44, and reflowed to fix the solder balls on the wiring pattern 40. As shown in FIG. The bumps may be formed by Ni plating and Au plating to form Ni-Au bumps.
상기한 바와 같이 처리한 웨이퍼를 슬라이스하여 각편의 반도체장치(30)를 형성한다.The wafer processed as described above is sliced to form each semiconductor device 30.
필요에 따라서는 반도체 장치(30)의 측면에 레지스트를 도포하고, 건조시켜 보호막(48)을 형성할 수 있다.If necessary, a resist may be applied to the side surface of the semiconductor device 30 and dried to form a protective film 48.
상기한 바와 같이 웨이퍼상에 동시에 제조해 넣음으로써, 한번에 다수의 반도체장치(30)를 형성할 수 있어 비용의 절감화를 도모할 수 있다.By simultaneously manufacturing the wafer on the wafer as described above, a plurality of semiconductor devices 30 can be formed at one time, and the cost can be reduced.
또, 웨이퍼를 슬라이스하여 각편의 반도체칩(32)으로 형성한 후, 상기와 같은 공정으로 반도체장치(30)로 완성시키더라도 좋다.Alternatively, the wafer may be sliced and formed into semiconductor chips 32 of each piece, and then the semiconductor device 30 may be completed by the above steps.
본 실시형태에서는 제1 절연피막(38) 및 제2 절연피막(42)을 형성하기 위해서 감광성 폴리이미드, 감광성 솔더레지스트를 사용했지만 이들 제1 절연피막(38), 제2 절연피막(42)으로서는 여러가지의 소재를 사용할 수 있고, 폴리이미드계 수지 외에 에폭시계 수지, 실리콘계 수지 등도 사용할 수 있고, 각 절연피막으로 적당한 수지를 선택하여 사용할 수 있다. 실리콘계 수지의 경우는 고무상의 탄성을 갖기 때문에, 특히 반도체칩과 실장기판의 사이에 생기는 응력을 완화시킬 수 있다.In the present embodiment, a photosensitive polyimide and a photosensitive solder resist are used to form the first insulating film 38 and the second insulating film 42, but as the first insulating film 38 and the second insulating film 42. Various materials can be used, epoxy resin, silicone resin, etc. can be used besides polyimide resin, and suitable resin can be selected and used for each insulating film. Since the silicone resin has rubbery elasticity, in particular, stresses generated between the semiconductor chip and the mounting substrate can be alleviated.
제3도에는 반도체장치 (30)의 제2 실시형태를 나타냈다.3 shows a second embodiment of the semiconductor device 30.
본 실시형태에서는, 복수의 반도체 칩(32)을 히트스프레더 등의 공통의 기판(47)상에 탑재하고, 상기 복수의 반도체칩(32)상에 상기와 동일한 공통의 제1 절연피막(38)을 형성하고, 상기 절연피막(38)상에 각 반도체칩(32)에 대응하는 각 배선패턴(40)과, 인접하는 반도체칩(32)을 전기적으로 접속하기 위한 전극(36)끼리간을 접속하는 배선패턴(45)을 상기 실시형태와 동일하게 형성하고, 그 위에 상기와 같이 공통의 제2 절연피막(42)을 형성하고, 각 배선패턴(40)의 외부접속단자 접합부(40a)에 범프(46)를 형성하도록 한 것이다.In this embodiment, the plurality of semiconductor chips 32 are mounted on a common substrate 47 such as a heat spreader, and the same first insulating film 38 as described above on the plurality of semiconductor chips 32. A connection between the wiring patterns 40 corresponding to the semiconductor chips 32 and the electrodes 36 for electrically connecting the adjacent semiconductor chips 32 on the insulating film 38. The wiring pattern 45 to be formed is formed in the same manner as in the above embodiment, a common second insulating film 42 is formed thereon as described above, and the bumps are formed on the external connection terminal junctions 40a of the respective wiring patterns 40. (46) was formed.
즉 복수의 반도체칩(32)을 사용하여 1개의 반도체장치(30)로 형성한 것이다.In other words, the semiconductor device 30 is formed by using the plurality of semiconductor chips 32.
복수의 반도체칩(32)으로서는, 예를 들어 MPU와 캐시메모리, 복수의 메모리끼리를 연접시킬 수 있다.As the plurality of semiconductor chips 32, for example, an MPU, a cache memory, and a plurality of memories can be connected to each other.
본 실시형태에서는 복수의 반도체 칩을 공통의 기판상에 형성하여 접속패드간을 전기적으로 접속했기 때문에 배선을 짧게 할 수 있어, 신호의 지연방지 등의 전기적 특성이 우수한 반도체 장치(멀티칩 모듈)를 제공할 수 있다. 또 제1 및 제2 절연피막을 공통으로 형성함으로써 제조도 용이해진다. 또 복수의 반도체칩(32) 측면을 공통의 프레임 (도시하지 않음)으로 유지하면 반도체칩을 공통의 기판(47)상에 실장할 필요가 없다. 또 복수의 반도체칩을 공통의 웨이퍼상에 형성할 수 있다.In this embodiment, since a plurality of semiconductor chips are formed on a common substrate and electrically connected between the connection pads, wiring can be shortened, and a semiconductor device (multi-chip module) having excellent electrical characteristics such as signal delay prevention can be provided. Can provide. Also, by forming the first and second insulating films in common, the production also becomes easy. If the plurality of semiconductor chips 32 side surfaces are held in a common frame (not shown), the semiconductor chips do not need to be mounted on the common substrate 47. In addition, a plurality of semiconductor chips can be formed on a common wafer.
본 실시형태의 반도체장치(30)도 상기와 같은 공정으로 제조할 수 있다.The semiconductor device 30 of the present embodiment can also be manufactured in the same manner as described above.
제4도는 상기한 반도체장치의 제조공정에서, 투공(44)내에 땜납 볼(범프(46))을 배치하여 배선패턴(40)상에 고정할 때에, 투공(44)의 내면 및 투공(44)의 가장자리에 미리 랜드(50)를 설비하고 나서 땜납 볼을 고정한 예를 나타낸다. 랜드(50)를 형성하기 위해서는, 투공(44)을 갖는 제2 절연피막(42)을 형성한 후, 절연피막(42) 표면에 동 등을 스퍼터링하여 금속층을 형성하고, 포토리소그래피 공정에 의해서 투공(44)의 내부와 가장자리 부만 금속층이 남도록 에칭하면 좋다. 렌드(50)는 저면에서 배선패턴(40)의 외부단자 접합부(40a)에 접속하여 투공(44)의 내벽면 및 가장자리부를 피복함으로써, 투공(44)에 랜드(50)를 설비하지 않은 경우와 비교하여, 땜납 볼(범프(46))이 투공(44)의 내면전체와 접합되어 확실하게 부착된다. 또, 땜납 볼과 배선패턴(40)과의 전기적 도통이 확실하게 된다.4 shows the inner surface of the hole 44 and the hole 44 when the solder ball (bump 46) is placed in the hole 44 and fixed on the wiring pattern 40 in the above-described manufacturing process of the semiconductor device. The example which fixed the solder ball after installing the land 50 in advance at the edge of this is shown. In order to form the lands 50, after forming the second insulating film 42 having the perforations 44, a metal layer is formed by sputtering copper or the like on the surface of the insulating film 42, and through the photolithography process. It is good to etch so that only the inside and the edge part of 44 may leave a metal layer. The lend 50 is connected to the external terminal junction portion 40a of the wiring pattern 40 at the bottom thereof to cover the inner wall surface and the edge portion of the perforation 44, so that the land 50 is not provided in the perforation 44. In comparison, the solder balls (bumps 46) are joined to the entire inner surface of the perforations 44 and securely attached. In addition, electrical conduction between the solder ball and the wiring pattern 40 is ensured.
또, 금속층을 에칭하여 랜드(50)를 형성한 후, 랜드(50)의 표면에 보호도금으로서 니켈도금, 금도금을 행하면 보다 더 확실히 범프(46)를 접합할 수 있다.After the land layer 50 is formed by etching the metal layer, the bumps 46 can be more reliably bonded by nickel plating and gold plating on the surface of the land 50 as protective plating.
제5도는 배선패턴(40)을 다층 형성한 반도체장치의 예를 나타낸 것이다. 이 실시형태의 반도체장치는 제1 절연피막(38)과 제2 절연피막(42)에 더하여, 제3의 절연피막(52)과 제4의 절연피막(54)을 갖는다. 제2 절연피막(42) 표면에는 제1 절연피막(38)의 표면에 설비한 배선패턴(40)과 전기적으로 도통하는 배선패턴 (40b)이 설비되고, 제3의 절연피막(52) 표면에는 배선패턴(40b)과 전기 적으로 도통하는 배선패턴(40c)이 설비되어 있다. 제4의 절연피막(54)에는 배선패턴(40c)에 전기적으로 도통해서 랜드(50)가 부착되고, 상기 랜드(50)에는 범프(46)가 접합되어 있다.5 shows an example of a semiconductor device in which the wiring pattern 40 is formed in multiple layers. The semiconductor device of this embodiment has a third insulating film 52 and a fourth insulating film 54 in addition to the first insulating film 38 and the second insulating film 42. On the surface of the second insulating film 42, a wiring pattern 40b electrically connected to the wiring pattern 40 provided on the surface of the first insulating film 38 is provided, and on the surface of the third insulating film 52. The wiring pattern 40c is electrically provided with the wiring pattern 40b. The land 50 is attached to the fourth insulating film 54 by electrically conducting the wiring pattern 40c, and the bumps 46 are bonded to the land 50.
각 층간의 배선패턴(40)을 전기적으로 접속하는 방법으로서는, 상술한 실시형태로 제1 절연피막(38)과 제2 절인피막(42)을 형성하고 배선패턴(40)과 랜드(50)를 접속하는 방법을 그대로 적용할 수 있다. 즉, 절연피막을 형성하기 위해서 폴리이미드계 또는 에폭시계 등의 감광성 레지스트를 도포하고, 노광, 현상함으로써 층간에서 배선패턴(40)을 접속하는 부위에 투공을 형성한 후, 절연피막의 표면에 동 등의 도체금속을 스퍼터링 또는 증착에 의해서 형성하고, 이렇게 형성된 도체층을 에칭함으로써 하층의 배선패턴(40)과 전기적으로 접속하면서 배선패턴을 형성한다.As a method of electrically connecting the wiring pattern 40 between the layers, the first insulating film 38 and the second cut film 42 are formed in the above-described embodiment, and the wiring pattern 40 and the land 50 are formed. The method of connecting can be applied as it is. That is, in order to form an insulating film, a photosensitive resist such as polyimide or epoxy is coated, exposed and developed to form a perforation in a portion connecting the wiring pattern 40 between the layers, and then coated on the surface of the insulating film. Conductor metals, such as these, are formed by sputtering or vapor deposition, and the wiring layer is formed by electrically connecting with the wiring pattern 40 of the lower layer by etching the conductor layer thus formed.
다음 층에 대해서도, 동일하게 상기 절연피막상에 감광성 레지스트를 도포하고, 표면을 평탄으로 한 후 노광, 현상하여 투공을 형성하고, 절연피막상에 도체층을 형성하고 에칭하여 상기 층위에 배선패턴을 형성한다.Also for the next layer, a photosensitive resist was applied on the insulating film in the same manner, and the surface was flattened, followed by exposure and development to form perforations. Form.
이와 같이 절연피막을 거쳐서 전기적 도통을 유지하면서 배선패턴(40)을 다층으로 형성할 수 있다. 제5도에 나타낸 실시형태에서는 최외층인 제4 절연피막(54)에 랜드(50)를 형성하여 땜납 볼(범프(46))을 접합하고 있다.In this way, the wiring pattern 40 can be formed in multiple layers while maintaining the electrical conduction through the insulating film. In the embodiment shown in FIG. 5, the land 50 is formed in the 4th insulating film 54 which is an outermost layer, and the solder ball (bump 46) is joined.
이와 같이 배선패턴(40)을 다층 형성함으로써 배선패턴(40)을 형성하는 자유도가 크게 된다.By forming the wiring pattern 40 in multiple layers in this manner, the degree of freedom for forming the wiring pattern 40 is increased.
제6도는 배선패턴(40)을 다층 형성한 경우의 응용예로서, 콘덴서(56) 또는 저항(58)인 회로용 소자를 조립한 예를 나타낸다. 배선패턴(40)을 다층 형성한 경우는 이와 같이 회로용 소자를 조립하는 것이 용이하여 보다 다용도의 반도체장치로서 제공할 수 있다. 콘덴서나 저항은 스퍼터링 등의 박막공정에 의해 제작해 넣을 수 있다.FIG. 6 shows an example of assembling a circuit element, which is a capacitor 56 or a resistor 58, as an application example when the wiring pattern 40 is formed in multiple layers. In the case where the wiring patterns 40 are formed in multiple layers, the circuit elements can be easily assembled in this way, and thus they can be provided as more versatile semiconductor devices. A capacitor and a resistor can be produced by a thin film process such as sputtering.
상술한 각 반도체장치의 제조공정에서는 절연피막을 형성하기 위해서 감광성 레지스트를 사용하여, 포토리소그래피 공정에 의해 절연피막에 투공(44)을 형성하거나 절연피막의 표면에 배선패턴을 형성할 수도 있다. 이 포토리소그래피 공정에서는 노광하는 데 자외선이 사용되므로 실제의 반도체장치의 제조공정에서는 자외선의 노광에 의해서 반도체소자에 형성된 회로가 손상되지 않도록 할 필요가 있다. 또, 이 자외선에 의한 노광이 반도체칩에 악영향을 미치는 것은 네거티브형의 감광성 레지스트를 사용하는 경우이다.In the above-described manufacturing process of each semiconductor device, in order to form an insulating film, a photosensitive resist may be used to form a hole 44 in the insulating film by a photolithography process or a wiring pattern may be formed on the surface of the insulating film. In this photolithography step, ultraviolet light is used to expose the light. In the actual manufacturing process of the semiconductor device, it is necessary to ensure that the circuit formed on the semiconductor element is not damaged by exposure to ultraviolet light. Incidentally, this exposure to ultraviolet rays adversely affects the semiconductor chip when a negative photosensitive resist is used.
네거티브형의 감광성 레지스트에서는 노광한 부위가 현상시에는 용해되지 않는 부위가 되므로 노광할 때에는 후공정에서 용해제거하는 부위를 마스크하여, 최종적으로 남는 부위를 노광한다. 예를 들면, 제7도에 나타낸 바와 같이 비활성화막(34)상에 제1 절연피막(38)을 형성하는 경우에는 감광성 레지스트를 도포한 후, Al 패드(36)를 마스크하고, 그 이외의 범위를 노광하게 된다. 이 때문에 마스크한 Al 패드(36)이외의 범위에 자외선이 조사되어, 감광성 레지스트와 비활성화막(34)을 통해서 반도체칩 (32) 표면까지 자외선이 투과하고, 이것에 의해서 반도체칩(32)이 손상되는 경우가 있다.In the negative photosensitive resist, the exposed portion becomes a portion that does not dissolve during development, so that during exposure, the portion to be dissolved and removed in a later step is masked and the remaining portion is exposed. For example, when forming the 1st insulating film 38 on the passivation film 34 as shown in FIG. 7, after apply | coating a photosensitive resist, the Al pad 36 is masked and the other range Will be exposed. For this reason, ultraviolet rays are irradiated to a range other than the masked Al pad 36, and ultraviolet rays are transmitted to the surface of the semiconductor chip 32 through the photosensitive resist and the passivation film 34, thereby damaging the semiconductor chip 32. It may become.
또, 포지티브형의 감광성 레지스트는 노광된 부위가 용해 제거된다. 따라서, 상기한 제1 절연피막(38)에 Al 패드(36)의 부분에 투공을 형성하는 예로서는 감광성 레지스트를 도포한 후, Al 패드(36) 이외의 범위를 마스크하고, Al 패드(36) 부분에만 자외선을 조사한다. Al 패드(36)의 부분에는 회로가 형성되어 있지 않기 때문에, 이 자외선조사에 의해서 반도체칩(32) 회로가 손상될 우려가 없다. 또, 제1 절연피막(38)이나 제2 절연피막(42) 표면에 배선패턴(40)을 형성하기 위한 포토리소그래피 공정에서도, 포지리브형의 감광성 레지스트를 사용하는 경우에는, 반드시 배선패턴(40)을 형성하기 위한 동층 등의 금속층이 하지에 있는 부분에 자외선조사를 행하므로, 반도체칩(32) 회로가 손상될 우려는 없다.In addition, in the positive photosensitive resist, the exposed portion is removed by dissolution. Therefore, as an example of forming a hole in the Al pad 36 in the above-described first insulating film 38, a photosensitive resist is applied, and then, a range other than the Al pad 36 is masked, and the Al pad 36 is partly formed. Only irradiate ultraviolet rays. Since no circuit is formed in the portion of the Al pad 36, there is no fear that the semiconductor chip 32 circuit will be damaged by the ultraviolet irradiation. In the photolithography step for forming the wiring pattern 40 on the surface of the first insulating film 38 or the second insulating film 42, the wiring pattern 40 must be used when a positive rib type photosensitive resist is used. UV irradiation is applied to a portion where a metal layer, such as a copper layer, for forming a) is underneath, so that the circuit of the semiconductor chip 32 is not damaged.
상기한 네거티브형의 감광성 레지스트를 사용하는 포토리소그래피 공정에서 반도체칩(32)이 손상되는 것을 방지하는 방법으로서는, 제8도에 나타낸 바와 같이 비활성화막(34)의 표면에 포토리소그래피 공정에서 사용하는 자외선을 차폐하는 자외선 차폐층(60)을 설비하는 방법이 유효하다.As a method of preventing the semiconductor chip 32 from being damaged in the photolithography process using the above-described negative photosensitive resist, as shown in FIG. 8, ultraviolet rays used in the photolithography process on the surface of the passivation film 34 The method of installing the ultraviolet-ray shielding layer 60 which shields | drains is effective.
자외선 차폐층(60)은 반도체칩(32)에 형성된 회로를 자외선으로부터 보호하는 것으로서, 제8도에 나타낸 바와 같이 Al 패드 (36)를 제외 한 범위에 대해서 제1 절연피막(38)을 형성하기 전에 설비한다. 자외선 차폐층(60)은 Cr 금속층, Cu 금속층, 또는 Cr 금속층-Ni 금속층-Cu 금속층 등의 복수의 금속층으로 형성한다. Cr 금속층을 사용하는 경우에는 0.1정도의 두께로도 충분히 자외선 차폐의 기능이 있다.The ultraviolet shielding layer 60 protects the circuit formed on the semiconductor chip 32 from ultraviolet rays, and as shown in FIG. Before installation. The ultraviolet shielding layer 60 is formed of a plurality of metal layers such as a Cr metal layer, a Cu metal layer, or a Cr metal layer, a Ni metal layer, and a Cu metal layer. 0.1 when using a Cr metal layer The thickness of the degree is enough to function as a UV shield.
자외선 차폐층(60)을 형성하는 경우에는, 우선 반도체칩(32)의 비활성화막(34)상에 스퍼터링 또는 증착 등에 의해서 Cr 금속층 등을 형성하고, 그 표면에 Al 패드(36)부분만 노출시킨 레지스트 패턴을 형성하고, 레지스트패턴을 마스크로 하여 Cr 금속층 등을 에칭함으로써 형성한다.In the case of forming the ultraviolet shielding layer 60, first, a Cr metal layer or the like is formed on the passivation film 34 of the semiconductor chip 32 by sputtering or vapor deposition, and only the Al pad 36 is exposed on the surface thereof. A resist pattern is formed, and it forms by etching a Cr metal layer etc. using a resist pattern as a mask.
상기한 자외선 차폐층(60)을 설비해 놓으면, 네거티브형의 감광성 레지스트를 사용하여 절연피막을 형성하는 경우에서도 포토리소그래피 공정에서 반도체칩(32)이 자외선에 의해서 손상을 받을 우려가 없고, 임의의 패턴으로 자외선을 조사할 수 있다. 제9도는, 제1 절연피막(38)을 형성하기 위해서 네거티브형의 감광성 레지스트를 도포하이 노광하고 있는 상태를 나타낸다. 감광성 레지스트의 하층에 설비한 자외선 차폐층(60)에 의해서 자외선이 차폐되어 반도체칩(32) 회로를 보호하여 노광할 수 있다.If the above-mentioned ultraviolet shielding layer 60 is provided, there is no risk that the semiconductor chip 32 may be damaged by ultraviolet rays in the photolithography process even when an insulating film is formed using a negative photosensitive resist. Ultraviolet rays can be irradiated with a pattern. FIG. 9 shows a state where the negative photosensitive resist is applied and exposed to form the first insulating film 38. Ultraviolet rays are shielded by the ultraviolet shielding layer 60 provided under the photosensitive resist, and the semiconductor chip 32 circuit can be protected and exposed.
제1 절연피막(38)의 표면에 배선패턴(40)을 설비한 후, 그 위에 제2절연피막(42)을 형성하는 경우의 노광에 대해서도 동일하다.The same applies to the exposure in the case where the wiring pattern 40 is provided on the surface of the first insulating film 38 and the second insulating film 42 is formed thereon.
제10도는 제4도에 나타낸 반도체장치의 형성예로 자외선 차폐층(60)을 설비하여 얻어진 반도체장치를 나타내고 있다. 제4도에 나타낸 실시형태와는 비활성화막(34)상에 자외선 차폐층(60)을 설비한 점만 다르다. 배선패턴(40)을 다층 형성하는 반도체장치의 경우도 동일하게 자외선 차폐층(60)을 설비하여 형성할 수 있다. 또, 자외선 차폐층(60)을 설비한 경우라도 물론 네거티브형의 감광성 레지스트에 한정되지 않고 포지티브형의 감광성 레지스트를 사용해도 좋다.FIG. 10 shows a semiconductor device obtained by providing the ultraviolet shielding layer 60 as an example of formation of the semiconductor device shown in FIG. It differs only from the embodiment shown in FIG. 4 by providing the ultraviolet shielding layer 60 on the passivation film 34. In the case of a semiconductor device in which the wiring pattern 40 is formed in multiple layers, the ultraviolet shielding layer 60 may be provided in the same manner. Moreover, even when the ultraviolet shielding layer 60 is provided, it is a matter of course that it is not limited to the negative photosensitive resist, You may use a positive photosensitive resist.
본 발명에 의한 반도체장치에 의하면, 상술한 바와 같이 인터포저로 된 제1 및 제2 절연피막을 얇게 형성할 수 있기 때문에, 얇은 반도체장치로 형성할 수 있고 비용의 절감화도 도모할 수 있다.According to the semiconductor device according to the present invention, since the first and second insulating films made of the interposer can be formed thin as described above, the semiconductor device can be formed into a thin semiconductor device and the cost can be reduced.
제1,제2 절연피막은 경도가 그렇게 높지 않기 때문에, 반도체칩 표면을 보호하거나, 반도체 칩과 실장기판의 사이에 생기는 응력을 완화하는 완충층으로서도 기능한다.Since the first and second insulating films are not so high in hardness, they function as a buffer layer to protect the surface of the semiconductor chip or to relieve stress generated between the semiconductor chip and the mounting substrate.
또 복수의 반도체칩의 소요의 전극을 전기적으로 접속함으로써 신호의 지연방지 등의 전기적 특성의 향상을 도모하고, 또 제1 및 제2 절연피막을 공통으로 형성함으로써 제조도 용이해지는 효과를 거둘 수 있다.In addition, by electrically connecting the required electrodes of a plurality of semiconductor chips, it is possible to improve the electrical characteristics such as preventing signal delay, and to form the first and second insulating films in common, thereby facilitating the production. .
또, 본 발명에 의한 반도체장치의 제조방법에 의하면, 칩사이즈의 반도체장치를 용이하고 또 확실히 얻을 수 있고, 배선패턴을 다층 형성함으로써 배선패턴을 형성하는 자유도를 증대시킬 수 있으며, 자외선 차폐층을 설비함으로써 특히 네거티브형의 감광성 레지스트를 사용하여 제조하는 경우에 현저한 효과를 거둘 수 있다.In addition, according to the method for manufacturing a semiconductor device according to the present invention, it is possible to obtain a chip size semiconductor device easily and reliably, and by forming a wiring pattern in multiple layers, the degree of freedom for forming the wiring pattern can be increased. By the provision, a remarkable effect can be attained especially in the case of manufacturing using a negative photosensitive resist.
Claims (15)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6560795 | 1995-03-24 | ||
| JP95-065607 | 1995-03-24 | ||
| JP25986195A JP3356921B2 (en) | 1995-03-24 | 1995-10-06 | Semiconductor device and method of manufacturing the same |
| JP95-259861 | 1995-10-06 |
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| Publication Number | Publication Date |
|---|---|
| KR960036009A KR960036009A (en) | 1996-10-28 |
| KR100216642B1 true KR100216642B1 (en) | 1999-09-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960007924A KR100216642B1 (en) | 1995-03-24 | 1996-03-22 | Semiconductor device and method of manufacture of the same |
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| Country | Link |
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| JP (1) | JP3356921B2 (en) |
| KR (1) | KR100216642B1 (en) |
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| KR100746862B1 (en) | 2000-04-19 | 2007-08-07 | 도요 고한 가부시키가이샤 | Semiconductor device and fabrication method therefor |
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| JP3068534B2 (en) * | 1997-10-14 | 2000-07-24 | 九州日本電気株式会社 | Semiconductor device |
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| JP2002094082A (en) | 2000-07-11 | 2002-03-29 | Seiko Epson Corp | Optical element and its manufacturing method and electronic equipment |
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| JP3939504B2 (en) * | 2001-04-17 | 2007-07-04 | カシオ計算機株式会社 | Semiconductor device, method for manufacturing the same, and mounting structure |
| JP4217639B2 (en) | 2004-02-26 | 2009-02-04 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
| JP4265575B2 (en) | 2005-06-21 | 2009-05-20 | セイコーエプソン株式会社 | Semiconductor chip and electronic equipment |
| JP4238843B2 (en) | 2005-06-21 | 2009-03-18 | セイコーエプソン株式会社 | Semiconductor chip, semiconductor chip manufacturing method, and electronic device |
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| JP4607152B2 (en) * | 2007-07-09 | 2011-01-05 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device |
| US9704769B2 (en) | 2014-02-27 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP) |
-
1995
- 1995-10-06 JP JP25986195A patent/JP3356921B2/en not_active Expired - Fee Related
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- 1996-03-22 KR KR1019960007924A patent/KR100216642B1/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100746862B1 (en) | 2000-04-19 | 2007-08-07 | 도요 고한 가부시키가이샤 | Semiconductor device and fabrication method therefor |
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| Publication number | Publication date |
|---|---|
| KR960036009A (en) | 1996-10-28 |
| JP3356921B2 (en) | 2002-12-16 |
| JPH08330313A (en) | 1996-12-13 |
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