KR960030082A - RAM access unit in the hard disk controller - Google Patents

RAM access unit in the hard disk controller Download PDF

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KR960030082A
KR960030082A KR1019950000179A KR19950000179A KR960030082A KR 960030082 A KR960030082 A KR 960030082A KR 1019950000179 A KR1019950000179 A KR 1019950000179A KR 19950000179 A KR19950000179 A KR 19950000179A KR 960030082 A KR960030082 A KR 960030082A
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South Korea
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register
address
ram
input
decoder
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KR0146194B1 (en
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정호창
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device
    • G06F3/0676—Magnetic disk device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

데이터래치 클럭신호가 입력되면 순차적으로 램 어드레스 상위비트, 램 어드레스 중위비트, 램 데이터를 출력하는 제1레지스터(21)와, 어드레스래치 클럭신호가 입력되면 순차적으로 AH 레지스터 어드레스, AM 레지스터 어드레스, 램 어드레스하위비트를 출력하는 제2레지스터(22)와, 제2레지스터로부터 입력되는 AH 레지스터 어드레스, AM 레지스터 어드레스에따라 AH 레지스터와 AM 레지스터를 인에이블시키기 위한 신호를 출력하는 디코더(23)와, 디코더의 출력신호를 시스템 클럭 신호와 동기시키기 위한 다수개의 논리곱 수단(G21~G24)과, 디코더에 의해 인에이블되면 제1레지스터로부터 입력되는램 어드레스 상위비트를 저장하는 AH 레지스터(25)와, 디코더에 의해 인에이블되면 제1레지스터로부터 입력되는 램 어드레스 중위비트를 저장하 AM 레지스터(26)와, 멀티플렉서 선택신호가 입력되면 제1레지스터로부터 입력되는 램 데이터를출력하는 제1멀티플렉서(28)와, 멀티플렉서 선택신호가 입력되면 제2레지스터로부터 입력되는 램 어드레스 하위비트를출력하는 제2멀티플렉서(29)로 구성되며, 3사이클에 걸쳐 램을 액세스함으로써 램 액세스 시간을 단축시킬 수가 있는하드 디스크 컨트롤러의 램 액세스 장치를 제공한다.When the data latch clock signal is input, the first register 21 which outputs the RAM address upper bit, the RAM address middle bit, and RAM data sequentially, and when the address latch clock signal is input, the AH register address, AM register address, RAM A second register 22 for outputting the address lower bits, a decoder 23 for outputting a signal for enabling the AH register and the AM register according to the AH register address and AM register address inputted from the second register, and a decoder; A plurality of logical multiplication means (G21 to G24) for synchronizing the output signal with the system clock signal, an AH register 25 for storing the upper order bits of the RAM address input from the first register when enabled by the decoder, and the decoder When enabled by the AM register 26 to store the RAM address intermediate bit input from the first register, The first multiplexer 28 outputs RAM data input from the first register when the multiplexer selection signal is input, and the second multiplexer 29 outputs the RAM address low bit input from the second register when the multiplexer selection signal is input. The present invention provides a RAM access device of a hard disk controller that can reduce RAM access time by accessing RAM over three cycles.

Description

하드 디스크 컨트롤러의 램 액세스 장치RAM access unit in the hard disk controller

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 이 발명의 실시예에 따른 하드 디스크 컨트롤러의 램 액세스 장치의 상세 회로도이다.2 is a detailed circuit diagram of the RAM access device of the hard disk controller according to the embodiment of the present invention.

Claims (4)

데이터래치 클럭신호가 입력되면 순차적으로 램 어드레스 상위비트, 램 어드레스 중위비트, 램 데이터를출력하는 제1레지스터와, 어드레스래치 클럭신호가 입력되면 순차적으로 AH 레지스터 어드레스, AM 레지스터 어드레스, 램 어드레스 하위비트를 출력하는 제2레지스터와, 상기한 제2레지스터로부터 입력되는 AH 레지스터 어드레스, AM 레지스터 어드레스에 따라 AH 레지스터와 AM 레지스터를 인에이블시키기 위한 신호를 출력하는 디코더와, 상기한 디코더의 출력신호를 시스템 클럭 신호와 동기시키기 위한 다수개의 논리곱 수단과, 상기한 디코더에 의한 인에이블되면, 상기한 제1레지스터로부터 입력되는 램 어드레스 상위비트를 저장하는 AH 레지스터와, 상기한 디코더에 의해 인에이블되면, 상기한 제1레지스터로부터 입력되는 램 어드레스 중위비트를 저장하는 AM 레지스터와, 멀티플렉서 선택신호가 입력되면, 상기한 제1레지스터로부터 입력되는 램 데이터를 출력하는 제1멀티플렉서와, 멀티플렉서 선택신호가 입력되면, 상기한 제2레지스터로부터 입력되는 램 어드레스 하위비트를 출력하는 제2멀티플렉서로 이루어지는 것을 특징으로 하는 하드 디스크컨트롤러의 램 액세스 장치.When the data latch clock signal is input, the upper order of the RAM address, the RAM address middle bit, and the first register to output the RAM data, and when the address latch clock signal is input, the AH register address, AM register address, and RAM address lower bit. And a decoder for outputting a signal for enabling the AH register and the AM register according to the AH register address and the AM register address inputted from the second register, and the output signal of the decoder. A plurality of logical and logical means for synchronizing with a clock signal, an AH register storing RAM address higher bits input from the first register when enabled by the decoder, and when enabled by the decoder, RAM address median ratio input from the first register A first multiplexer for outputting RAM data input from the first register when the multiplexer selection signal is input and a multiplexer selection signal is input, and a lower RAM address input from the second register when the multiplexer selection signal is input. And a second multiplexer for outputting bits. 제1항에 있어서, 상기한 논리곱 수단의 출력단에 클럭단자가 연결되어 있고 상기한 제1레지스터의 출력단에 입력단이 연결되어 있는 제3레지스터와, 상기한 논리곱 수단의 출력단에 클럭단자가 연결되어 있고 상기한 제1레지스터의 출력단에 입력단이 연결되어 있는 AL 레지스터를 더 포함하여 이루어지는 것을 특징으로 하는 하드 디스크 컨트롤러의 램 액세스 장치.The third terminal of claim 1, wherein a clock terminal is connected to the output terminal of the logical multiplication unit and an input terminal is connected to the output terminal of the first register, and a clock terminal is connected to the output terminal of the logical multiplication unit. And an AL register having an input terminal coupled to an output terminal of the first register. 제1항 또는 제2항에 있어서, 상기한 하드 디스크 컨트롤러의 램 액세스 장치는 8비트 버스를 통해서 구성소자가 연결되는 것을 특징으로 하는 하드 디스크 컨트롤러의 램 액세스 장치.The RAM access apparatus of claim 1 or 2, wherein the RAM access apparatus of the hard disk controller is connected to a component through an 8-bit bus. 제1항 또는 제2항에 있어서, 상기한 논리곱 수단은 AND 게이트로 이루어지는 것을 특징으로 하는 하드 디스크 컨트롤러의 램 액세스 장치.The RAM access apparatus according to claim 1 or 2, wherein the AND product comprises an AND gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950000179A 1995-01-06 1995-01-06 RAM access unit in the hard disk controller Expired - Fee Related KR0146194B1 (en)

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KR1019950000179A KR0146194B1 (en) 1995-01-06 1995-01-06 RAM access unit in the hard disk controller

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KR1019950000179A KR0146194B1 (en) 1995-01-06 1995-01-06 RAM access unit in the hard disk controller

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KR960030082A true KR960030082A (en) 1996-08-17
KR0146194B1 KR0146194B1 (en) 1998-09-15

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