KR960027739A - Transmission buffer insertion path of SSCOP sublayer - Google Patents

Transmission buffer insertion path of SSCOP sublayer Download PDF

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Publication number
KR960027739A
KR960027739A KR1019940038188A KR19940038188A KR960027739A KR 960027739 A KR960027739 A KR 960027739A KR 1019940038188 A KR1019940038188 A KR 1019940038188A KR 19940038188 A KR19940038188 A KR 19940038188A KR 960027739 A KR960027739 A KR 960027739A
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KR
South Korea
Prior art keywords
pointer
ram
buffer
value
transmission buffer
Prior art date
Application number
KR1019940038188A
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Korean (ko)
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KR0133803B1 (en
Inventor
윤성욱
Original Assignee
배순훈
대우전자 주식회사
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Priority to KR1019940038188A priority Critical patent/KR0133803B1/en
Publication of KR960027739A publication Critical patent/KR960027739A/en
Application granted granted Critical
Publication of KR0133803B1 publication Critical patent/KR0133803B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 SSCOP 계층의 전송버퍼 삽입회로에 관한것으로, 입력된 포인터 값에 의해 전송버퍼의 어느 한 램을 지시하게 된N개의 램지스터의(10)와; 외부로부터 기록신호가 입력되면 현재 저장된 램레지스터의 포인터값을 축력하게 된 버퍼포인트터(12); 상기 버퍼포인트(12)의 출력값에 의해 소정의 램레지스터(10)의 포인터를 읽어 출력하게 된 디먹스(14); 상기 디먹스 출력값을 입력받아 전송버퍼의 해당 램에 데이타를 쓰도록 제어신호를 출력하게 된 CPU(18); 상기 CPU의 제어신호에의해 소정 메세지를 저장하게 된 전송버퍼(20) 및; 상기 CPU(18)의 제어신호에 의해 버퍼포인터의 값을 1 증가시킨 가산기(22)로 구성된 것으로, 램레지스터에 소정 메세지를 저장하는 램의 포인터를 저장할 뿐 아니라 전송버퍼를 구성하는 램을 제어하여 상기 메세지를 저장하도록 제어하게 해주는 것이다.The present invention relates to a transmission buffer insertion circuit of an SSCOP layer, comprising: 10 of N ram registers indicating one of the transmission buffers by an input pointer value; A buffer pointer 12 that accumulates a pointer value of a currently stored RAM register when a recording signal is input from the outside; A demux 14 which reads and outputs a pointer of a predetermined RAM register 10 based on the output value of the buffer point 12; A CPU 18 receiving the demux output value and outputting a control signal to write data to a corresponding RAM of a transmission buffer; A transmission buffer 20 for storing a predetermined message by a control signal of the CPU; It consists of an adder 22 which increases the value of the buffer pointer by one by the control signal of the CPU 18, and not only stores a pointer of a RAM storing a predetermined message in a RAM register but also controls a RAM constituting a transfer buffer. To control the storage of the message.

Description

SSCOP 부계층의 전송버퍼 삽입경로Transmission buffer insertion path of SSCOP sublayer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 SSCOP 부계층의 전송버퍼 삽입 회로를 도시한 구성블럭도이다.4 is a block diagram showing a transmission buffer insertion circuit of an SSCOP sublayer according to the present invention.

Claims (1)

입력된 포인터값에 의해 전송버퍼의 어느 한 램을 지시하게 된 N개의 램레지스터(10)와; 외부로 부터 기록신호가 입력되면 현재 저장된 램레지스터의 포인터값을 출력하게 된 버퍼포인터(12); 상기 버퍼포이터(12)의 출력값에 의해 소정의 램레지스터(10)의 포인터를 읽어 출력하게 된 디먹스(14); 상기 디먹스의 출력값을 입력받아 전송버퍼의 해당램에 데이타를 쓰도록 제어신호를 출력하게 된 CPU(18); 상기 CPU의 제어신호에 의해 소정 메세지를 저장하게 된 전송버퍼(20) 및; 상기 CPU(18)의 제어신호에 의해 버퍼포인터의 값을 1 증가시키게 된 가산기(22)로 구성된 SSCOP 부계층의 전송버퍼 삽입회로.N RAM registers 10 indicating one RAM of the transmission buffer by the input pointer value; A buffer pointer 12 which outputs a pointer value of a currently stored RAM register when a recording signal is input from the outside; A demux 14 for reading and outputting a pointer of a predetermined RAM register 10 based on the output value of the buffer pointer 12; A CPU 18 receiving the output value of the demux and outputting a control signal to write data to a corresponding RAM of a transmission buffer; A transmission buffer 20 for storing a predetermined message by the control signal of the CPU; And an adder (22) for increasing the value of the buffer pointer by one control signal of the CPU (18). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038188A 1994-12-28 1994-12-28 A circuit inserting data into send buffer of sscop sublayer KR0133803B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038188A KR0133803B1 (en) 1994-12-28 1994-12-28 A circuit inserting data into send buffer of sscop sublayer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038188A KR0133803B1 (en) 1994-12-28 1994-12-28 A circuit inserting data into send buffer of sscop sublayer

Publications (2)

Publication Number Publication Date
KR960027739A true KR960027739A (en) 1996-07-22
KR0133803B1 KR0133803B1 (en) 1998-04-27

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ID=19404447

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038188A KR0133803B1 (en) 1994-12-28 1994-12-28 A circuit inserting data into send buffer of sscop sublayer

Country Status (1)

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KR (1) KR0133803B1 (en)

Also Published As

Publication number Publication date
KR0133803B1 (en) 1998-04-27

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