KR960015573A - Somewhat FIFO and pad erasing circuit using it - Google Patents

Somewhat FIFO and pad erasing circuit using it Download PDF

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Publication number
KR960015573A
KR960015573A KR1019940028198A KR19940028198A KR960015573A KR 960015573 A KR960015573 A KR 960015573A KR 1019940028198 A KR1019940028198 A KR 1019940028198A KR 19940028198 A KR19940028198 A KR 19940028198A KR 960015573 A KR960015573 A KR 960015573A
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KR
South Korea
Prior art keywords
somewhat
output
fifo
pad
erase
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Application number
KR1019940028198A
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Korean (ko)
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KR0129175B1 (en
Inventor
윤성욱
Original Assignee
배순훈
대우전자 주식회사
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Priority to KR1019940028198A priority Critical patent/KR0129175B1/en
Publication of KR960015573A publication Critical patent/KR960015573A/en
Application granted granted Critical
Publication of KR0129175B1 publication Critical patent/KR0129175B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H04L2012/5657—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL3/4

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 다소거 FIFO 및 이를 이용한 패드 삭제회로에 관한 것으로, 램(2)과; 라이트신호(wr)에 따라 포인터를 하나씩 증가시키고 입력된 데이타를 상기 램(12)에 저장시키는 라이트포인터 카운터(14); 리드신호(rd)에 따라 포인터를 하나씩 증가시키는 리드포인터 카운터(17); 외부로부터 입력된 소정의 데이타(ext_pnt)값에 상기 리드포인터 카운터(17)의 출력을 가산하는 가산기(18); 및 다소거 제어신호(erase)가 입력되면 상기 가산기(18)의 출력을 선택하고, 다소거제어신호(erase)가 입력되지 않으면 상기 리드포인터 카운터(17)의 출력을 선택하여 상기 램(12)에 저장된 데이타를 읽어내는 리드포인터 선택부(16)를 구비하여 소정의 데이타값만큼 한꺼번에 데이타를 삭제할 수 있다.The present invention is more or less related to a FIFO and a pad erase circuit using the same, including: a RAM (2); A write pointer counter 14 for incrementing a pointer one by one according to a write signal wr and storing the input data in the RAM 12; A lead pointer counter 17 for incrementing the pointers one by one according to the read signal rd; An adder 18 for adding the output of the lead pointer counter 17 to a predetermined value of ext_pnt input from the outside; And when the control signal erase is inputted somewhat, the output of the adder 18 is selected, and if the control signal erase is not inputted, the output of the lead pointer counter 17 is selected to be selected. The read point selector 16 which reads the data stored in the readout block 16 can delete data at a time by a predetermined data value.

Description

다소거 FIFO 및 이를 이용한 패드 삭제회로Somewhat FIFO and pad erasing circuit using it

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 다소거 FIFO를 이용한 패드 삭제회로를 도시한 블럭도.1 is a block diagram showing a pad erasing circuit using a somewhat FIFO according to the present invention.

Claims (3)

램(12)과; 라이트신호(wr)에 따라 포인터를 하나씩 증가시키고 입력된 데이타를 상기 램(12)에 저장시키는 라이트포인터 카운터(14); 리드신호(rd)에 따라 포인터를 하나씩 증가시키는 리드포인터 카운터(17); 외부로부터 입력된 소정의 데이타값(ext_pnt)에 상기 리드포인터 카운터(17)의 출력을 가산하는 가산기(18); 및 다소거 제어신호(erase)가 입력되면 상기 가산기(18)의 출력을 선택하고, 다소거 제어신호(rease)가 입력되지 않으면 상기 리드포인더 카운터(17)의 출력을 선택하여 상기 램(12)에 저장된 데이타를 읽어내는 리드포인터 선택부(16)를 구비한 것을 특징으로 하는 다소거 FIFO.Ram 12; A write pointer counter 14 for incrementing a pointer one by one according to a write signal wr and storing the input data in the RAM 12; A lead pointer counter 17 for incrementing the pointers one by one according to the read signal rd; An adder 18 for adding the output of the lead pointer counter 17 to a predetermined data value ext_pnt input from the outside; And when the control signal (erase) is inputted somewhat, the output of the adder 18 is selected, and when the control signal (rease) is inputted somewhat, the output of the lead pointer counter 17 is selected and the RAM 12 is selected. And a lead pointer selector 16 for reading data stored in the < RTI ID = 0.0 > 제1항에 있어서, 상기 리드포인터 선택부(16)는 멀티플랙서로 구현된 것을 특징으로 하는 다소거 FIFO.2. The FIFO of claim 1, wherein the lead pointer selector is implemented as a multiplexer. ATM통신방식의 AAL 3/4 프로토콜에 따른 패드 삭제회로에 있어서, 소정의 고정된 값에서 길이표시값을감산하여 패드길이를 구하는 감산기(20)와; 상기 감산기(20)의 출력과 다소거신호(erase)를 입력한 후 리드신호(rd)에 따른 패드를 삭제하는 다소거 FIFO(10)를 구비하는 것을 특징으로 하는 다소거 FIFO를 이용한 패드 삭제회로.A pad erasing circuit according to the AAL 3/4 protocol of the ATM communication system, comprising: a subtractor (20) for subtracting a length display value from a predetermined fixed value to obtain a pad length; A pad erasing circuit using a somewhat FIFO, characterized in that it comprises a somewhat FIFO (10) for deleting the pad according to the read signal (rd) after inputting the output of the subtractor 20 and the somewhat erase (erase). . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940028198A 1994-10-31 1994-10-31 A multi-erasable fifo & a circuit for erasing pads using the fifo KR0129175B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940028198A KR0129175B1 (en) 1994-10-31 1994-10-31 A multi-erasable fifo & a circuit for erasing pads using the fifo

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940028198A KR0129175B1 (en) 1994-10-31 1994-10-31 A multi-erasable fifo & a circuit for erasing pads using the fifo

Publications (2)

Publication Number Publication Date
KR960015573A true KR960015573A (en) 1996-05-22
KR0129175B1 KR0129175B1 (en) 1998-04-08

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KR1019940028198A KR0129175B1 (en) 1994-10-31 1994-10-31 A multi-erasable fifo & a circuit for erasing pads using the fifo

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KR0129175B1 (en) 1998-04-08

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