KR950009403A

KR950009403A - Digital Signal Processor Interface Device Using PIPO Memory

Info

Publication number: KR950009403A
Application number: KR1019930018445A
Authority: KR
Inventors: 김영우
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1993-09-14
Filing date: 1993-09-14
Publication date: 1995-04-21

Abstract

적어도 둘이상의 DSP를 포함하는 DSP인터페이스 장치에 있어서 부팅메모리로 FIFO메모리를 이용하여 로직의 구현을 단순화시킬 수 있는 피포메모리를 이용한 다수 디지틸 시그날 프로세서 인터페이스 장치가 개시되고 있다. 본 발명에 따르면 다수의 DSP의 초기 프로그램 로드를 위해 적어도 둘 이상의 FIFO를 사용함으로써 초기 프로그램의 변경이 용이하며, 초기 프로그램의 크기에 관계없이 FIFO의 저장용량을 선택할 수 있어 인터페이스 회로를 간단한 구성할 수 있다.A multi-digital signal processor interface device using a pico memory that can simplify the implementation of logic using a FIFO memory as a boot memory in a DSP interface device including at least two DSPs is disclosed. According to the present invention, the initial program can be easily changed by using at least two FIFOs for the initial program load of a plurality of DSPs, and the storage capacity of the FIFO can be selected regardless of the size of the initial program, thereby simplifying the interface circuit. have.

Description

Digital Signal Processor Interface Device Using PIPO Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래 롬을 이용한 디지털 시그날 프로세서의 인터페이스 장치 구성도,1 is a block diagram of an interface device of a digital signal processor using a conventional ROM;

제3도는 본 발명의 일 실시예에 따른 피포 메모리를 이용한 디지털 시그날 프로세서의 인터페이스 장치 구성도,3 is a configuration diagram of an interface device of a digital signal processor using a pico memory according to an embodiment of the present invention;

제5도는 상술한 제2도의 구성중 FIFO의 데이터 로드순서를 나타내는 메모리 맵,FIG. 5 is a memory map showing a data loading order of FIFOs in the configuration of FIG. 2 described above; FIG.

제6도는 본 발명의 일실시에에 따른 주요 동작신호의 타이밍도.6 is a timing diagram of a main operation signal according to an embodiment of the present invention.

Claims

A DSP interface device including at least two DSPs for loading an initial program and performing signal processing of an input signal, wherein the initial program data of the DSPs are accessed from an external storage device and the page length data of the initial program is in order from the last word. A CPU outputting one byte at a time, at least two FIFO memories for receiving and storing the initial program data from the CPU to load an initial program into a DSP, and loading the DSP and the FIFO in the data load state of the FIFO memory. A switching unit 140 for outputting a switching signal for controlling data input / output to the FIFO memory, a status unit for retrieving a data storage state of the FIFO memory and outputting respective status signals, and receiving the status signals from the FIFO Outputs a data input of a memory and decodes the status signal W decoder, and a digital signal processor interface device using the FIFO memory, characterized in that each input receives the signal processing data of the DSP configured as decoding logic for outputting to the CPU and outputting to the CPU.

※ Note: The disclosure is based on the initial application.