KR960027632A - Alarm display signal (AIS) detection circuit in DS3 communication system - Google Patents

Alarm display signal (AIS) detection circuit in DS3 communication system Download PDF

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Publication number
KR960027632A
KR960027632A KR1019940038651A KR19940038651A KR960027632A KR 960027632 A KR960027632 A KR 960027632A KR 1019940038651 A KR1019940038651 A KR 1019940038651A KR 19940038651 A KR19940038651 A KR 19940038651A KR 960027632 A KR960027632 A KR 960027632A
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KR
South Korea
Prior art keywords
signal
alarm display
display signal
ais
frame period
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Application number
KR1019940038651A
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Korean (ko)
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KR0135335B1 (en
Inventor
차재규
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박성규
대우통신 주식회사
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Priority to KR1019940038651A priority Critical patent/KR0135335B1/en
Publication of KR960027632A publication Critical patent/KR960027632A/en
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Publication of KR0135335B1 publication Critical patent/KR0135335B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector

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  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

본 발명은 디에스3(DS3)통신 시스템에서의 경보표시신호(AIS) 검출회로에 관한 것으로서 경보표시 신호(AIS) 발생용 오실레이터 출력신호를 입력으로 받아 DS3 신호의 비트마다 상기 오실레이터 출력신호의 1비트 폭으로 로우가 되는 DS3 1 프레임 주기 지정신호(MFEN)을 출력하는 프레임 주기 카운트 수단과; 상기 프레임 주기 카운트 수단으로부터 상기 MFEN을 입력받고 송신 및 수신 데이타에 동기된 클럭신호에 따라 송신 및 수신 NRZ 데이타의 '0'의 갯수를 계수하여 AIS 신호를 출력하는 제1 및 제2 AIS 검출수단을 포함하여 회로의 중복을 피하여 회로의 용량을 최소화한다.The present invention relates to an alarm display signal (AIS) detection circuit in a DS3 (DS3) communication system, and receives an oscillator output signal for generating an alarm display signal (AIS) as an input and 1 bit of the oscillator output signal for each bit of the DS3 signal. Frame period counting means for outputting a DS3 one frame period designation signal MFEN that becomes low in width; First and second AIS detection means for receiving the MFEN from the frame period counting means and counting the number of '0' of the transmitted and received NRZ data according to a clock signal synchronized with the transmitted and received data and outputting an AIS signal; Minimize the circuit's capacity by avoiding redundancy of the circuit.

Description

디에스3(DS3) 통신 시스템에서의 경보표시신호(AIS) 검출회로Alarm display signal (AIS) detection circuit in DS3 communication system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따른 경보표시신호(AIS) 검출회로도.1 is an alarm indication signal (AIS) detection circuit in accordance with the present invention.

Claims (2)

경보표시 신호 발생용 오실레이터 출력신호를 입력으로 받아 DS3 신호의 비트마다 상기 오실레이터 출력신호의 1비트 폭으로 로우가 되는 DS3 1 프레임 주기 지정신호를 출력하는 프레임 주기 카운트 수단과 ; 상기 프레임 주기카운트 수단으로부터 상기 DS3 1 프레임 주기 지정신호를 입력받고 송신 및 수신 데이타에 동기된 클럭신호에 따라 송신 및 수신 NRZ 데이타의 '0'의 갯수를 계수하여 경보표시 신호를 출력하는 제1 및 제2경보표시신호 검출수단을 포함하는 디에스3 통신 시스템에서의 경보표시신호 검출회로.Frame period counting means for receiving an oscillator output signal for generating an alarm display signal as an input and outputting a DS3 one frame period designation signal that goes low by one bit of the oscillator output signal for each bit of the DS3 signal; First and outputting an alarm display signal by receiving the DS3 1 frame period designation signal from the frame period counting means and counting the number of '0' of the transmission and reception NRZ data according to a clock signal synchronized with the transmission and reception data; An alarm display signal detection circuit in a DS3 communication system including a second alarm display signal detection means. 제1항에 있어서, 상기 제1 및 제2경보표시신호 검출수단은 송신 및 수신 NRZ데이타의 '0'의 갯수를 계수하여 '0'의 갯수가 7개 이하이면 경보표시신호를 출력하는 디에스3 통신 시스템에서의 경보표시신호 검출회로.The DS3 of claim 1, wherein the first and second alarm display signal detecting means counts the number of '0' of the transmission and reception NRZ data and outputs an alarm display signal when the number of '0' is 7 or less. Alarm display signal detection circuit in a communication system. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038651A 1994-12-29 1994-12-29 Circuit for detecting ais in ds3 system KR0135335B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038651A KR0135335B1 (en) 1994-12-29 1994-12-29 Circuit for detecting ais in ds3 system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038651A KR0135335B1 (en) 1994-12-29 1994-12-29 Circuit for detecting ais in ds3 system

Publications (2)

Publication Number Publication Date
KR960027632A true KR960027632A (en) 1996-07-22
KR0135335B1 KR0135335B1 (en) 1998-04-27

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Application Number Title Priority Date Filing Date
KR1019940038651A KR0135335B1 (en) 1994-12-29 1994-12-29 Circuit for detecting ais in ds3 system

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KR (1) KR0135335B1 (en)

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Publication number Publication date
KR0135335B1 (en) 1998-04-27

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