KR950024427A - Programmable Timeout Timer - Google Patents

Programmable Timeout Timer Download PDF

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Publication number
KR950024427A
KR950024427A KR1019940001682A KR19940001682A KR950024427A KR 950024427 A KR950024427 A KR 950024427A KR 1019940001682 A KR1019940001682 A KR 1019940001682A KR 19940001682 A KR19940001682 A KR 19940001682A KR 950024427 A KR950024427 A KR 950024427A
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KR
South Korea
Prior art keywords
signal
counting means
timeout timer
clock
input state
Prior art date
Application number
KR1019940001682A
Other languages
Korean (ko)
Other versions
KR960012470B1 (en
Inventor
최진국
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019940001682A priority Critical patent/KR960012470B1/en
Publication of KR950024427A publication Critical patent/KR950024427A/en
Application granted granted Critical
Publication of KR960012470B1 publication Critical patent/KR960012470B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

본 발명은 카운터의 비트수를 적게 사용하면서도 카운터의 출력과 이벤트 신호와의 시간 오차를 최소화할 수 있도록 하기 위하여, 입력되는 클럭수파수를 높여 카운터의 출력을 단시간 내에 동기시킴으로써 시간 오차를 줄이고, 클럭 분기회로를 사용하여 카운터의 비트수를 늘리지 않고 카운트다운된 출력을 발생시키도록 하는 타임아웃 타이머에 관한 기술이다.The present invention reduces the time error by synchronizing the output of the counter within a short time by increasing the input clock frequency in order to minimize the time error between the output of the counter and the event signal while using the number of bits of the counter. This technique relates to a timeout timer that uses a branch circuit to generate a counted down output without increasing the number of bits in the counter.

Description

프로그램 가능한 타임아웃 타이머Programmable Timeout Timer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 동기식 타임아웃 타이머의 실시예를 도시한 회로도.2 is a circuit diagram illustrating an embodiment of a synchronous timeout timer of the present invention.

제4도는 본 발명의 비동기식 타임아웃 타이머의 실시예를 도시한 회로도.4 is a circuit diagram illustrating an embodiment of the asynchronous timeout timer of the present invention.

Claims (3)

시스템 상에서 입력 상태의 변화를 감지하여 일정시간 동안만 인에이블된 타임아웃 신호를 출력하는 통상의 타임아웃 타이머에 있어서, 입력 상태의 변화를 검출한 로딩(loading) 신호에 의해 초기치를 전달받아 타임아웃 신호를 일정시간 동안 카운팅하여 출력하는 카운팅 수단과, 입력 상태의 변화가 없는 동안에는 타이머로 입력되는 높은 주파수의 동기 클럭을 상기 카운팅 수단으로 전달하고, 입력 상태가 변화하여 타임아웃 신호가 출력되는 동안에는 상기의 동기 클럭을 분주하여 상기 카운팅 수단에 전달하도록 하는 클럭 분주 수단을 포함하는 것을 특징으로하는 타임아웃 타이머.In a typical timeout timer that detects a change in an input state and outputs an enabled timeout signal only for a predetermined time, the system receives an initial value by a loading signal that detects a change in the input state, and then times out. A counting means for counting and outputting a signal for a predetermined time; and a high frequency synchronous clock input to a timer while the input state is unchanged, and transmitting the counted means to the counting means; And a clock divider means for dividing a synchronous clock of the clock signal to transmit the divided clocks to the counting means. 제1항에 있어서, 상기 클럭 분주 수단은 상기 카운팅 수단의 출력이 카운팅되어 제로 상태에 이르면 리셋되는 것을 특징으로 하는 타임아웃 타이머.The timeout timer according to claim 1, wherein said clock division means is reset when the output of said counting means is counted and reaches a zero state. 제1항에 있어서, 입력 상태의 변화를 검출하여 상기 카운팅 수단에 초기치를 로딩하는 신호를 발생시키기 위해, 반전 출력을 입력단으로 피드백시켜 연결한 디플립를롭을 사용하는 것을 특징으로 하는 타임아웃 타이머.2. The timeout timer according to claim 1, wherein a deflip connected by feeding back an inverting output to an input terminal is used to detect a change in an input state and generate a signal for loading an initial value into the counting means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940001682A 1994-01-31 1994-01-31 Programmable time-out timer KR960012470B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940001682A KR960012470B1 (en) 1994-01-31 1994-01-31 Programmable time-out timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940001682A KR960012470B1 (en) 1994-01-31 1994-01-31 Programmable time-out timer

Publications (2)

Publication Number Publication Date
KR950024427A true KR950024427A (en) 1995-08-21
KR960012470B1 KR960012470B1 (en) 1996-09-20

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940001682A KR960012470B1 (en) 1994-01-31 1994-01-31 Programmable time-out timer

Country Status (1)

Country Link
KR (1) KR960012470B1 (en)

Also Published As

Publication number Publication date
KR960012470B1 (en) 1996-09-20

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