KR870005525A - Signal Synchronization and Signal Separation Control Clock Generation Circuit - Google Patents

Signal Synchronization and Signal Separation Control Clock Generation Circuit

Info

Publication number
KR870005525A
KR870005525A KR1019850008533A KR850008533A KR870005525A KR 870005525 A KR870005525 A KR 870005525A KR 1019850008533 A KR1019850008533 A KR 1019850008533A KR 850008533 A KR850008533 A KR 850008533A KR 870005525 A KR870005525 A KR 870005525A
Authority
KR
South Korea
Prior art keywords
clock
signal
control
received data
circuit
Prior art date
Application number
KR1019850008533A
Other languages
Korean (ko)
Other versions
KR890000414B1 (en
Inventor
박용우
Original Assignee
강잔구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강잔구, 삼성반도체통신 주식회사 filed Critical 강잔구
Priority to KR1019850008533A priority Critical patent/KR890000414B1/en
Publication of KR870005525A publication Critical patent/KR870005525A/en
Application granted granted Critical
Publication of KR890000414B1 publication Critical patent/KR890000414B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Sub-Exchange Stations And Push- Button Telephones (AREA)

Abstract

내용 없음No content

Description

신호동기 및 신호분리 제어클럭 발생회로Signal Synchronization and Signal Separation Control Clock Generation Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 송수신데이터 구성도1 is a block diagram of transmission and reception data

제2도는 본발명에 따른 블럭도2 is a block diagram according to the present invention

제3도는 본 발명의 실시예의 구체회로도3 is a detailed circuit diagram of an embodiment of the present invention.

제4도 및 제5도는 제3도의 각 부분의 동작 파형도.4 and 5 are operational waveform diagrams of respective parts of FIG.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 수신세이터 검출회로 2 : 동기제어회로 3 : 카운터1: reception receiver detection circuit 2: synchronous control circuit 3: counter

4 : 디코우더 5 : 신호추출클럭발생회로 8 : 시프트레지스터4: Decoder 5: Signal Extraction Clock Generation Circuit 8: Shift Register

9,30,40,50 : 앤드게이트 10,20 : 제1, 2래치회로9,30,40,50: AND gate 10,20: 1st, 2nd latch circuit

Claims (1)

수신데이터를 입력하여 신호동기를 하며 수신데이터중 신호분리 제어클럭을 발생하는 회로에 있어서, 송신 인에이블 신호의 제어하에 수신데이터 및 클럭펄스(CKF)를 입력하여 수신데이터를 상기 클럭 펄스열로 검출 출력하는 수신데이터 검출회로(1)와 상기 송신 인에이블신호를 클럭펄스로 입력하고 상기 수신데이터 검출펄스열을 리세트신호로 입력하여 동기 제어신호를 출력하는 동기제어 회로(2)와 상기 동기 제어 신호를 리세트신호로 하여 입력클럭(CKF)를 카운팅하여 분주하므로서 클럭동기 및 동기된 분주클럭을 발생하는 카운터(3)와 상기 카운터(3)의 분주된 클럭을 입력하여 수신정보신호의 신호분리를 하게하는 제어클럭을 출력하는 디코우더(4)와 상기 제어클럭 및 카운터(3)에서 출력하는 소정의 클럭 및 동기제어회로(2)의 동기제어신호의 인버어트된 신호를 입력하여 동기비트, 프레임구분비트, 시그날비트 및 음성데이터 추출용 제어클럭과 음성데이터 추출용제어클럭 및 데이터추출용 제어클럭을 출력하는 신호추출클럭 발생회로(5)로 구성됨을 특징으로 하는 회로.A circuit for synchronizing signal by receiving received data and generating a signal separation control clock among received data, wherein the received data and the clock pulse (CKF) are inputted under the control of a transmit enable signal to detect and output the received data as the clock pulse string. A synchronous control circuit (2) for inputting the received data detection circuit (1) and the transmit enable signal as a clock pulse, and inputting the received data detection pulse string as a reset signal to output a synchronous control signal; As the reset signal, the input clock CKF is counted and divided so that the clock 3 and the divided clock of the synchronized clock are generated, and the divided clock of the counter 3 is input to separate the received information signal. Of the decoder 4 outputting the control clock and the predetermined clock outputted from the control clock and the counter 3 and the synchronization control signal of the synchronization control circuit 2; A signal extraction clock generation circuit (5) for inputting an inverted signal and outputting a control clock for synchronizing bits, frame division bits, signal bits, and voice data extraction, a control clock for voice data extraction, and a control clock for data extraction. Characterized by a circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850008533A 1985-11-14 1985-11-14 A circuit generating control clock in signal synchronism and decoding KR890000414B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850008533A KR890000414B1 (en) 1985-11-14 1985-11-14 A circuit generating control clock in signal synchronism and decoding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850008533A KR890000414B1 (en) 1985-11-14 1985-11-14 A circuit generating control clock in signal synchronism and decoding

Publications (2)

Publication Number Publication Date
KR870005525A true KR870005525A (en) 1987-06-09
KR890000414B1 KR890000414B1 (en) 1989-03-16

Family

ID=19243667

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850008533A KR890000414B1 (en) 1985-11-14 1985-11-14 A circuit generating control clock in signal synchronism and decoding

Country Status (1)

Country Link
KR (1) KR890000414B1 (en)

Also Published As

Publication number Publication date
KR890000414B1 (en) 1989-03-16

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