KR940017476A - Line Delay Compensation Circuit of Digital Transmission System - Google Patents

Line Delay Compensation Circuit of Digital Transmission System Download PDF

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Publication number
KR940017476A
KR940017476A KR1019920025727A KR920025727A KR940017476A KR 940017476 A KR940017476 A KR 940017476A KR 1019920025727 A KR1019920025727 A KR 1019920025727A KR 920025727 A KR920025727 A KR 920025727A KR 940017476 A KR940017476 A KR 940017476A
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KR
South Korea
Prior art keywords
output
counting
signal
data
demultiplexing
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Application number
KR1019920025727A
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Korean (ko)
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KR0142311B1 (en
Inventor
안규철
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정장호
금성정보통신 주식회사
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Priority to KR1019920025727A priority Critical patent/KR0142311B1/en
Publication of KR940017476A publication Critical patent/KR940017476A/en
Application granted granted Critical
Publication of KR0142311B1 publication Critical patent/KR0142311B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 고속 정송 시스템등과 같이 시스템과 모듈간의 신호를 일정한 시간에 동시에 처리하고자할 시 선로지연을 보상시키는 디지탈 전송시스템의 선로지연 보상회로에 관한 것으로서, 이러한 본 발명의 목적은 모듈에서 전송되는 신호를 수신하고 클럭, 데이타, 프레임 펄스를 검출하여 출력하는 상기 제1신호수단에서 출력된 프레임 펄스를 카운팅하는 기록카운팅수단, 상기 기록카운팅수단에서 출력된 값을 역다중화하는 역다중화수단과, 상기 역다중화수단에서 출력된 신호에 따라 상기 제1신호 수신수단에 출력된 데이타를 판독하는 일레스틱 저장수단과, 상기 모듈에서 전송되는 시스템 클럭 및 시스템 프레임 펄스를 카운팅하여 판독하는 판독카운팅수단과, 상기 판독카운팅수단에서 출력된 신호에 따라 상기 일레스틱 저장수단에서 출력된 데이타를 다중화하는 다중화수단과, 상기 모듈에서 전송되는 시스템 프레임 펄스를 검출하여 선로 지연에 따른 프레임 펄스를 보상하는 송신 프레임 펄스 생성수단과, 상기 다중화수단에서 출력된 데이타를 시스템 클럭에 동기화시켜 출력하는 데이타 재동기수단을 구비함으로써 달성된다.The present invention relates to a line delay compensation circuit of a digital transmission system that compensates for line delay when a signal between a system and a module is to be processed simultaneously at a predetermined time, such as a high speed transmission system. Recording counting means for counting frame pulses output from the first signal means for receiving a signal and detecting and outputting clock, data, and frame pulses; demultiplexing means for demultiplexing a value output from the recording counting means; An elastic storage means for reading data output to the first signal receiving means according to a signal output from the demultiplexing means, reading counting means for counting and reading a system clock and a system frame pulse transmitted from the module; Output from the elastic storage means according to the signal output from the reading counting means Multiplexing means for multiplexing data, transmission frame pulse generating means for detecting system frame pulses transmitted from the module and compensating frame pulses according to line delay, and synchronizing and outputting the data output from the multiplexing means to a system clock. This is achieved by including data resynchronization means.

Description

디지탈 전송시스템의 선로지연 보상회로Line Delay Compensation Circuit of Digital Transmission System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명 디지탈 전송시스템의 선로지연 보상회로도, 제4도는 제3도의 각부 입출력 파형도.3 is a line delay compensation circuit diagram of the digital transmission system of the present invention, and FIG. 4 is a part input / output waveform diagram of FIG.

Claims (1)

모듈에서 전송되는 신호를 수신하고 클럭, 데이타, 프레임 펄스를 검출하여 출력하는 제1신호수신수단과, 상기 제1신호수신수단에서 출력된 프레임 펄스를 카운팅하는 기록카운팅수단과, 상기 기록카운팅수단에서 출력된 값을 역다중화하는 역다중화수단과, 상기 역다중화수단에서 출력된 신호에 따라 상기 제1신호 수신수단에 출력된 데이타를 판독하는 일레스틱 저장수단과, 상기 모듈에서 전송되는 시스템 클럭 및 시스템 프레임 펄스를 카운팅하여 판독하는 판독카운팅수단과, 상기 판독카운팅수단에서 출력된 신호에 따라 상기 일레스틱 저장수단에서 출력된 데이타를 다중화하는 다중화수단과, 상기 모듈에서 전송되는 시스템 프레임 펄스를 검출하여 선로 지연에 따른 프레임 펄스를 보상하는 송신 프레임 펄스 생성수단과, 상기 다중화수단에서 출력된 데이타를 시스템 클럭에 동기화시켜 출력하는 데이타 재동기수단을 포함하여 된것을 특징으로한 디지탈 전송시스템의 선로지연 보상회로.A first signal receiving means for receiving a signal transmitted from the module and detecting and outputting a clock, data, and frame pulse, recording counting means for counting the frame pulse output from the first signal receiving means, and in the recording counting means, Demultiplexing means for demultiplexing the output value, elastic storage means for reading data output to the first signal receiving means according to a signal output from the demultiplexing means, a system clock and a system transmitted from the module Read counting means for counting and reading frame pulses, multiplexing means for multiplexing data output from the elastic storage means according to the signal output from the read counting means, and detecting and detecting a system frame pulse transmitted from the module Transmitting frame pulse generating means for compensating frame pulses according to a delay; And data resynchronization means for synchronizing the outputted data to a system clock and outputting the data. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920025727A 1992-12-28 1992-12-28 Delay compensation circuit for digital system KR0142311B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920025727A KR0142311B1 (en) 1992-12-28 1992-12-28 Delay compensation circuit for digital system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920025727A KR0142311B1 (en) 1992-12-28 1992-12-28 Delay compensation circuit for digital system

Publications (2)

Publication Number Publication Date
KR940017476A true KR940017476A (en) 1994-07-26
KR0142311B1 KR0142311B1 (en) 1998-07-01

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Application Number Title Priority Date Filing Date
KR1019920025727A KR0142311B1 (en) 1992-12-28 1992-12-28 Delay compensation circuit for digital system

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100739822B1 (en) * 2006-08-08 2007-07-13 한국표준과학연구원 A synchronization method of remote clock by using pulse second

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100739822B1 (en) * 2006-08-08 2007-07-13 한국표준과학연구원 A synchronization method of remote clock by using pulse second

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Publication number Publication date
KR0142311B1 (en) 1998-07-01

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