KR940012951A

KR940012951A - Frame Synchronization Circuit and Method of Digital Communication System

Info

Publication number: KR940012951A
Application number: KR1019920020925A
Authority: KR
Inventors: 함명식
Original assignee: 정용문; 삼성전자 주식회사
Priority date: 1992-11-09
Filing date: 1992-11-09
Publication date: 1994-06-24

Abstract

독립동기방식으로 운용되는 디지털 통신시스템에서 입력되는 수신데이타로 부터 프레임클럭을 발생시켜 일레스틱 버퍼에 저장하였다가 수신시스템에서 자체 발생시킨 시스템클럭 및 프레임동기신호를 기준으로 데이타를 리드함에 따라 리드하는 데이타 스트림을 감시할 수 없으므로 오동작이 발생하는 것을 방지한다.The frame clock is generated from the received data input from the digital communication system operated by the independent synchronous method and stored in the elastic buffer, and the data is read based on the system clock and the frame sync signal generated by the receiving system. Since data streams cannot be monitored, malfunctions are prevented from occurring.

이를 위하여 수신되는 다중화된 수신데이타를 수신클럭에 의해 일시 정지하고 저장된 데이타를 소정의 리드클럭에 의해 출력한다. 그리고 상기 출력 데이타로부터 프레임배열신호를 검출하며, 상기 프레임배열신호에 의해 정확한 프레임채널을 검출한다. 상기 프레임동기 검출 결과에 따라 상기 저장된 데이타를 리드하기 위한 리드클럭을 발생한다.To this end, the received multiplexed reception data is paused by the reception clock and the stored data are output by a predetermined read clock. The frame array signal is detected from the output data, and the correct frame channel is detected by the frame array signal. According to the frame synchronization detection result, a read clock for reading the stored data is generated.

따라서 수신시스템의 프레임동기 펄스신호로 프레임배열번호를 검출하여 프레임동기상태를 정확하게 유지하게 된다.Therefore, the frame alignment number is detected by the frame synchronization pulse signal of the receiving system to accurately maintain the frame synchronization state.

Description

Frame Synchronization Circuit and Method of Digital Communication System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명에 따른 프레임동기회로의 블록구성도,5 is a block diagram of a frame synchronization circuit according to the present invention;

제6도는 본 발명에 따른 제5도중 일레스틱 버퍼부(100) 및 MLS 검출부(102)의 구체회로도,6 is a detailed circuit diagram of the elastic buffer unit 100 and the MLS detection unit 102 of FIG. 5 according to the present invention;

제7도는 본 발명에 따른 제5도중 프레임동기 검출부(104) 및 리드클럭 발생부(110)의 구체회로도,7 is a detailed circuit diagram of the frame sync detector 104 and the lead clock generator 110 of FIG. 5 according to the present invention;

제8도는 제7도의 각 부분의 동작파형도.8 is an operational waveform diagram of each part of FIG.

Claims

In the frame synchronization of a digital communication system operating in an independent synchronous manner, an elastic buffer means for temporarily storing received multiplexed reception data by a reception clock and outputting the stored data by a predetermined read clock, and the elastic buffer Maximum long array detection means for detecting a frame array signal from the output data of the means; And a read clock generating means for generating a read clock for reading the stored data of the elastic buffer means.

A frame synchronization method of a digital communication system operating in an independent synchronous manner, the method comprising: a storing process of temporarily storing received multiplexed reception data by a reception clock and outputting the stored data by a predetermined read clock; Reading data stored in the storage process according to a maximum long array detection process for detecting a frame array signal, a frame sync detection process for detecting an accurate frame channel by the frame array signal, and a detection result of the frame sync detection process Frame synchronization method of a digital communication system, characterized in that consisting of a lead clock generation process for generating a lead clock for.

※ Note: The disclosure is based on the initial application.