KR890010793A - Digital Video Data Synchronization Detection Circuit of Digital Audio Tape Recorder - Google Patents

Digital Video Data Synchronization Detection Circuit of Digital Audio Tape Recorder Download PDF

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Publication number
KR890010793A
KR890010793A KR870013814A KR870013814A KR890010793A KR 890010793 A KR890010793 A KR 890010793A KR 870013814 A KR870013814 A KR 870013814A KR 870013814 A KR870013814 A KR 870013814A KR 890010793 A KR890010793 A KR 890010793A
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KR
South Korea
Prior art keywords
data
synchronization
output
synchronization data
synchronous
Prior art date
Application number
KR870013814A
Other languages
Korean (ko)
Other versions
KR910003371B1 (en
Inventor
정일석
Original Assignee
안시환
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 안시환, 삼성전자 주식회사 filed Critical 안시환
Priority to KR1019870013814A priority Critical patent/KR910003371B1/en
Priority to US07/267,334 priority patent/US5093750A/en
Priority to JP63280247A priority patent/JP2527468B2/en
Priority to GB8825983A priority patent/GB2212359B/en
Publication of KR890010793A publication Critical patent/KR890010793A/en
Application granted granted Critical
Publication of KR910003371B1 publication Critical patent/KR910003371B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
    • G11B5/09—Digital recording

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  • Television Signal Processing For Recording (AREA)

Abstract

내용 없음No content

Description

디지탈 오디오 테이프 레코더의 디지탈 비디오 데이타 동기 검출회로Digital Video Data Synchronization Detection Circuit of Digital Audio Tape Recorder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따른 블록도.1 is a block diagram according to the present invention.

제 2 도는 본 발명에 따른 제 1 도의 구체회로도.2 is a detailed circuit diagram of FIG. 1 according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 동기검출부 10, 20 : 제 1, 2 동기데이타 결정부1: Sync detector 10, 20: 1st, 2 sync data determiner

30 : 동기데이타 듀레이션 발생기 40, 50 : 제 1, 2 동기데이타 카운터30: Synchronization data duration generator 40, 50: First and second synchronization data counter

70, 80 : 제 1, 2 비교기 90 : 합산기70, 80: 1st, 2nd comparator 90: summer

100 : 인에이블 스위칭회로 110 : 디멀티플렉셔100: enable switching circuit 110: demultiplexer

Claims (1)

디지탈 오디오 테이프의 디지탈 비디오 데이타 동기검출 회로에 있어서, 디지탈 오디오 테이프상의 동기 및 비디오 데이타와 오디오 데이타로부터 동기데이타(7FFF)를 검출하는 동기검출부(1)와, 상기 동기검출부(1)로부터 제 1 동기데이타(7FFF)를 결정하는 제 1 동기데이타 결정부(10)와, 상기 동기검출부(1)의 출력으로부터 제 2 동기데이타(8000)를 결정하는 제 2 동기데이타 결정부(20)와, 상기 제 1 동기데이타 결정부(20)의 동기데이타를 받아 소정기간 듀레이션이 발생되는 동기데이타 듀레이션 발생회로(30)와, 상기 제 1 동기데이타 결정부(10)의 동기데이타(7FFF) 출력을 카운트하는 제 1 동기데이타카운터(40)와, 상기 동기데이타 듀레이션 발생기(30)의 출력과 상기 제 2 동기데이타 결정부(20)의 출력에 의해 카운팅 인에이블 신호를 발생하는 카운터 인에이블 회로(60)와, 상기 카운터 인에이블 회로(60)의 출력에 의해 제 2 동기데이타 결정부(20)의 출력 동기데이타(8000)를 카운트 하는 제 2 동기데이타 카운터(50)와, 상기 제 2 동기 데이타 카운터(40, 50)의 출력과 기준값을 비교하는 제 1, 2 비교기 (70, 80)와 상기 제 1, 2 비교기(70, 80)의 출력을 합산하여 원하는 동기 입력이 제 대로 이루어졌는가를 결정하는 제 1, 2 합산기(90)와, 상기 동기데이타 튜레이션 발생기(30) 클럭과 상기 합산기(90)의 동기데이타 입력완료 신호를 입력하여 메모리(램) 어드레싱 인에이블 신호를 발생하고 비디오 데이타 출력을 메모리로 전환하기 위해 제어신호를 발생하도록 스위칭 신호를 발생하는 인에이블 스위칭회로(100)와, 상기 인에이블 스위칭회로(100)의 출력에 의해 비디오와 오디오를 선택하여 출력하는 디멀티 플렉셔(110)로 구성됨을 특징으로 하는 회로.A digital video data synchronization detection circuit of a digital audio tape, comprising: a synchronization detection unit (1) for detecting synchronization on a digital audio tape and synchronization data (7FFF) from video data and audio data, and a first synchronization from the synchronization detection unit (1). A first synchronous data determination unit 10 for determining data 7FFF, a second synchronous data determination unit 20 for determining second synchronous data 8000 from the output of the synchronous detection unit 1, and the first 1. A synchronization data duration generation circuit 30 which receives the synchronization data of the first synchronization data determination unit 20 and generates a duration for a predetermined period, and counts the output of the synchronization data 7FFF of the first synchronization data determination unit 10. A counter enable for generating a counting enable signal by the first synchronization data counter 40, the output of the synchronization data duration generator 30, and the output of the second synchronization data determiner 20. FIG. A second synchronization data counter 50 for counting the output synchronization data 8000 of the second synchronization data determining unit 20 by the output of the circuit 60 and the counter enable circuit 60; and the second synchronization data counter 50; Is the desired synchronization input properly made by summing the outputs of the first and second comparators 70 and 80 comparing the output of the synchronous data counters 40 and 50 with the reference values? The first and second summers 90 to determine the first and second synchronization data generator 30 clocks and the synchronous data input completion signal of the summer 90 are input to generate a memory (RAM) addressing enable signal. And an output switching circuit 100 that selects and outputs video and audio by an output of the enable switching circuit 100 and a switching signal to generate a control signal to convert the video data output into a memory. Consists of a multiplexer 110 Circuit according to claim. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870013814A 1987-11-06 1987-12-04 Digital video data synchronizing detecting circuit for digital audio tape recorder KR910003371B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019870013814A KR910003371B1 (en) 1987-12-04 1987-12-04 Digital video data synchronizing detecting circuit for digital audio tape recorder
US07/267,334 US5093750A (en) 1987-11-06 1988-11-04 System for recording/reproducing video data on or from a tape medium for storing digital signals and method therein
JP63280247A JP2527468B2 (en) 1987-11-06 1988-11-05 Video data recording / reproducing apparatus and system using digital signal recording tape
GB8825983A GB2212359B (en) 1987-11-06 1988-11-07 Video recording/reproducing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870013814A KR910003371B1 (en) 1987-12-04 1987-12-04 Digital video data synchronizing detecting circuit for digital audio tape recorder

Publications (2)

Publication Number Publication Date
KR890010793A true KR890010793A (en) 1989-08-10
KR910003371B1 KR910003371B1 (en) 1991-05-28

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ID=19266625

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870013814A KR910003371B1 (en) 1987-11-06 1987-12-04 Digital video data synchronizing detecting circuit for digital audio tape recorder

Country Status (1)

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KR (1) KR910003371B1 (en)

Also Published As

Publication number Publication date
KR910003371B1 (en) 1991-05-28

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