KR960027271A

KR960027271A - Digital filter with FIR structure

Info

Publication number: KR960027271A
Application number: KR1019940038090A
Authority: KR
Inventors: 안종영
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1994-12-28
Filing date: 1994-12-28
Publication date: 1996-07-22

Abstract

1. 청구범위 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

탭계수를 승산하기 위한 승산기의 출력을 위치에 따라 지연시켜 디지탈 필터링하는 기술이다.It is a technique of digital filtering by delaying the output of a multiplier for multiplying tap coefficients by position.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

탭계수에 대응하는 수만큼 승산기를 구비하여야 하므로 회로가 복잡해지고 비용이 상승되는 문제를 해결한다.Since the number of multipliers corresponding to the tap coefficients must be provided, the circuit is complicated and the cost is increased.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

디지탈 필터에서 각 탭계수가 승산된 다수의 신호를 각각 지연시켜 대칭되는 신호를 생성하여 필터링함으로, 탭계수를 승산하기 위한 승산기의 갯수를 절반으로 줄인다.In the digital filter, a plurality of signals multiplied by each tap coefficient are delayed to generate and filter a symmetric signal, thereby reducing the number of multipliers used to multiply the tap coefficient by half.

4. 발명의 중요한 용도4. Important uses of the invention

디지탈신호의 필터링에 적용한다.Applies to the filtering of digital signals.

Description

Digital filter with FIR structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 디지탈 필터의 회로도.2 is a circuit diagram of a digital filter according to the present invention.

Claims

In a digital filter having an FIR structure, N + 1 multipliers (M ₀ -M _n ) for multiplying and outputting N + 1 tap coefficients (C ₀ -C _n ), respectively, and the multiplier (M ₀ ) N-adders B ₁ -B _{n for} adding each signal multiplied by ₀ -M _n-1 and a plurality of predetermined delayed signals, respectively, and connected to each other before and after the adders B ₁ -B _n . Multiplied by N + 1 delayers E ₀ -E _n for outputting the adder output signals of the adders B ₁ -B _n by a predetermined delay and outputting the multiplier M ₀ -M _n . N + 1 adders A ₀ -A _{n for} adding and outputting a predetermined delayed signal from a signal and a predetermined delayer E _n , respectively, and connected to the front and rear of the adder A ₀ -A _n , respectively. A digital filter comprising N delayers (D ₁ -D _n ) for outputting the delayed output signals of (A ₀ -B _n-1 ) by predetermined delays, respectively.

In a digital filter having an FIR structure, N + 1 multipliers (M ₀ -M _n ) for multiplying and outputting N + 1 tap coefficients (C ₀ -C _n ), respectively, and the multiplier (M ₀ ) _n ) is connected to the input of the delay (E ₀ ), the output of the multiplier (M ₀ -M _n-1 ) is connected to the input of the N adders (B ₁ -B _n ), respectively, the delay The output terminal of the group M _{0 is} connected to the output terminal of the adder B ₁ , and the delayers E ₁ -E _n-1 are connected between the adders B ₁ -B _n , respectively, and the multiplier M _0- M _n ) output terminals of N + 1 adders A ₀ -A _n are respectively connected to the output terminals of the adder B _n , and an input terminal of the delay unit E _n is connected to the output terminals of the adder B _n . An output terminal of the group E _n is connected to an input terminal of the adder A ₀ , and a delay unit D ₁ -E _n is connected between the N + 1 adders A ₀ -A _n , respectively. Digital filter.

※ Note: The disclosure is based on the initial application.