KR960027271A - Digital filter with FIR structure - Google Patents

Digital filter with FIR structure Download PDF

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Publication number
KR960027271A
KR960027271A KR1019940038090A KR19940038090A KR960027271A KR 960027271 A KR960027271 A KR 960027271A KR 1019940038090 A KR1019940038090 A KR 1019940038090A KR 19940038090 A KR19940038090 A KR 19940038090A KR 960027271 A KR960027271 A KR 960027271A
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KR
South Korea
Prior art keywords
adders
digital filter
adder
outputting
multiplier
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Application number
KR1019940038090A
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Korean (ko)
Inventor
안종영
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019940038090A priority Critical patent/KR960027271A/en
Publication of KR960027271A publication Critical patent/KR960027271A/en

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Abstract

1. 청구범위 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

탭계수를 승산하기 위한 승산기의 출력을 위치에 따라 지연시켜 디지탈 필터링하는 기술이다.It is a technique of digital filtering by delaying the output of a multiplier for multiplying tap coefficients by position.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

탭계수에 대응하는 수만큼 승산기를 구비하여야 하므로 회로가 복잡해지고 비용이 상승되는 문제를 해결한다.Since the number of multipliers corresponding to the tap coefficients must be provided, the circuit is complicated and the cost is increased.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

디지탈 필터에서 각 탭계수가 승산된 다수의 신호를 각각 지연시켜 대칭되는 신호를 생성하여 필터링함으로, 탭계수를 승산하기 위한 승산기의 갯수를 절반으로 줄인다.In the digital filter, a plurality of signals multiplied by each tap coefficient are delayed to generate and filter a symmetric signal, thereby reducing the number of multipliers used to multiply the tap coefficient by half.

4. 발명의 중요한 용도4. Important uses of the invention

디지탈신호의 필터링에 적용한다.Applies to the filtering of digital signals.

Description

에프아이알(FIR) 구조형태를 갖는 디지탈 필터Digital filter with FIR structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 디지탈 필터의 회로도.2 is a circuit diagram of a digital filter according to the present invention.

Claims (2)

FIR구조 형태를 갖는 디지탈 필터에 있어서, 데이타를 각각 입력받아 N+1개의 탭계수(C0-Cn)를 각각 승산 출력하기 위한 N+1개의 승산기(M0-Mn)와, 상기 승산기(M0-Mn-1)로부터 승산출력된 각 신호와 소정 지연된 다수의 신호를 각각 가산하여 출력하는 N개의 가산기(B1-Bn)와, 상기 가산기(B1-Bn)의 전후로 각각 연결되어 상기 가산기(B1-Bn)의 가산 출력신호를 소정 지연시켜 출력하기 위한 N+1개의 지연기(E0-En)와, 상기 승산기(M0-Mn)로부터 승산출력된 각 신호와 소정 지연기(En)으로 부터 소정지연된 신호를 각각 가산하여 출력하는 N+1개의 가산기(A0-An)와, 상기 가산기(A0-An)의 전후로 각각 연결되어 상기 가산기(A0-Bn-1)의 가산 출력 신호를 각각 소정 지연시켜 출력하기 위한 N개의 지연기(D1-Dn)로 구성함을 특징으로 하는 디지탈 필터.In a digital filter having an FIR structure, N + 1 multipliers (M 0 -M n ) for multiplying and outputting N + 1 tap coefficients (C 0 -C n ), respectively, and the multiplier (M 0 ) N-adders B 1 -B n for adding each signal multiplied by 0 -M n-1 and a plurality of predetermined delayed signals, respectively, and connected to each other before and after the adders B 1 -B n . Multiplied by N + 1 delayers E 0 -E n for outputting the adder output signals of the adders B 1 -B n by a predetermined delay and outputting the multiplier M 0 -M n . N + 1 adders A 0 -A n for adding and outputting a predetermined delayed signal from a signal and a predetermined delayer E n , respectively, and connected to the front and rear of the adder A 0 -A n , respectively. A digital filter comprising N delayers (D 1 -D n ) for outputting the delayed output signals of (A 0 -B n-1 ) by predetermined delays, respectively. FIR 구조 형태를 갖는 디지탈 필터에 있어서, 데이타를 각각 입력받아 N+1개의 탭계수(C0-Cn)를 각각 승산 출력하기 위한 N+1개의 승산기(M0-Mn)와, 상기 승산기(Mn)의 출력단이 지연기(E0)의 입력단에 연결되고, 상기 승산기(M0-Mn-1)의 출력단에 N개의 가산기(B1-Bn)의 입력단이 각각 연결되며, 상기 지연기(M0)의 출력단이 상기 가산기(B1)의 출력단에 연결되고, 상기 가산기(B1-Bn)간에 지연기(E1-En-1)가 각각 연결되며, 상기 승산기(M0-Mn)의 출력단에 N+1개의 가산기(A0-An)의 입력단이 각각 연결되며, 상기 가산기(Bn)의 출력단에 지연기(En)의 입력단이 연결되고, 상기 지연기(En)의 출력단이 상기 가산기(A0)의 입력단에 연결되며, 상기 N+1개의 가산기(A0-An)간에 지연기(D1-En)가 각각 연결됨을 특징으로 하는 디지탈 필터.In a digital filter having an FIR structure, N + 1 multipliers (M 0 -M n ) for multiplying and outputting N + 1 tap coefficients (C 0 -C n ), respectively, and the multiplier (M 0 ) n ) is connected to the input of the delay (E 0 ), the output of the multiplier (M 0 -M n-1 ) is connected to the input of the N adders (B 1 -B n ), respectively, the delay The output terminal of the group M 0 is connected to the output terminal of the adder B 1 , and the delayers E 1 -E n-1 are connected between the adders B 1 -B n , respectively, and the multiplier M 0- M n ) output terminals of N + 1 adders A 0 -A n are respectively connected to the output terminals of the adder B n , and an input terminal of the delay unit E n is connected to the output terminals of the adder B n . An output terminal of the group E n is connected to an input terminal of the adder A 0 , and a delay unit D 1 -E n is connected between the N + 1 adders A 0 -A n , respectively. Digital filter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038090A 1994-12-28 1994-12-28 Digital filter with FIR structure KR960027271A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100573277B1 (en) * 2000-11-24 2006-04-24 한국전자통신연구원 Multi-function Pulse Shaping Filter
KR100654188B1 (en) * 2004-06-30 2006-12-05 한국전자통신연구원 FIR filter realized on DSP and method for realizing the same
KR100678566B1 (en) * 2000-06-30 2007-02-05 마쯔시다덴기산교 가부시키가이샤 Amplitude detecting circuit
KR100689963B1 (en) * 2006-06-13 2007-03-08 김봉주 Spacer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100678566B1 (en) * 2000-06-30 2007-02-05 마쯔시다덴기산교 가부시키가이샤 Amplitude detecting circuit
KR100573277B1 (en) * 2000-11-24 2006-04-24 한국전자통신연구원 Multi-function Pulse Shaping Filter
KR100654188B1 (en) * 2004-06-30 2006-12-05 한국전자통신연구원 FIR filter realized on DSP and method for realizing the same
KR100689963B1 (en) * 2006-06-13 2007-03-08 김봉주 Spacer

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