KR100654188B1 - FIR filter realized on DSP and method for realizing the same - Google Patents

Abstract

The present invention relates to the implementation of a pulse shaping FIR filter of a transmitter in a digital communication system, and utilizes a feature of zero padding in implementing a filter implemented in an existing ASIC on a DSP.

More specifically, since zero padding occurs when the filter is implemented on the DSP, unnecessary operations are generated so that the operation of the filter to obtain an output value by performing the operation on the actual data value is performed by reducing the DSP load according to the operation. The present invention relates to a method for optimizing a filter which can obtain an optimum performance of the filter in time.

DSP, zero padding, FIR filter, soft pipeline, optimization, filter coefficients

Description

FIR filter realized on DSP and method for realizing the same}

1 is a view showing the structure of a typical FIR filter.

2 is a diagram illustrating a process of a filter using zero padding.

3 is a diagram illustrating rearranging filter coefficients according to an embodiment of the present invention.

4 is a diagram illustrating rearrangement of input values according to an embodiment of the present invention.

5 is a view showing a filter structure according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a finite impulse response filter (hereinafter, simply referred to as FIR). Specifically, a transmitter in a digital communication system transmits a signal by pulse shaping digital data into an analog wave form. The present invention relates to a method for optimizing a filter in implementing a pulse shaping FIR filter to be used on a DSP.

Conventional pulse shaping FIR has been implemented in ASIC, and optimization of FIR using symmetric properties has been proposed. This enabled real-time implementation in terms of speed. However, it is true that corresponding hardware is required when an interface with various functions is required in one system. In this case, the system grows in size, but when faced with the need to reconfigure a system to keep pace with rapidly changing technologies, ASICs are almost impossible to reconfigure, and they have to be rebuilt again. Inefficient

Therefore, as a method of solving the above-described points, SDR (Software Defined Radio) technology is recently used a lot. SDR technology supports the change of the system module through simple software upgrade by changing the hardware part of the system to software. The biggest feature is that the system can be reconfigured.

However, the reconfiguration of the system is possible if most of the blocks of the system are implemented in software, and generally can be implemented in an FPGA or a DSP. However, implementations in an FPGA take up most of the implementation on a DSP because reconfiguration takes longer than that in a DSP.

The feature of the DSP chip is to minimize the processing time of the multiplication using a soft pipeline, for example, to operate in the 16-bit unit having the minimum operation time and have the minimum operation time. Therefore, to take advantage of the soft pipeline's characteristics, instead of accepting and using one input value for each processing step, it takes inputs in blocks and stores them in a buffer, and then loads and multiplies the input data at once. The time is shortened.

With the advantages of DSP chips as described above, recent software has also been programmed for DSP, and the use of DSP features has also increased in the implementation of filters on DSP chips. Therefore, optimization of the filter operation time, which takes the largest load in implementing the FIR filter on the DSP chip, is required.

Therefore, in the present invention, in implementing the pulse shaping filter of the transmitter in software, in particular, the operation of the filter is minimized by using the property of zero padding when implementing on a DSP. This paper provides a method of implementing a filter that can obtain the optimal performance in the filter operation time when the pulse shaping FIR filter is implemented in software.

A filter implementation method according to an aspect of the present invention for achieving the above object, in an environment having L input block size, M filter tap number and N oversampling size, (a) to omit zero padding operation Repeatedly rearranging the input data value of the filter by a first unit corresponding to a value M / N obtained by dividing a filter tap number by an oversampling size; (b) calculating the input data values constituting the first unit with corresponding filter coefficients and sequentially outputting the number N times; (c) rearranging the filter coefficients so that the input data values of the first unit can be sequentially input; And (d) shifting the input data values one by one and repeatedly outputting the steps (a) and (b) L times.

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In addition, in a method of implementing a FIR filter having L input block sizes, M filter taps, and N oversampling sizes on a DSP, (a) in order to omit zero padding operations, the input data value of the filter is determined by the number of filter taps. Repeating rearrangement N times in a first unit corresponding to the value M / N divided by the oversampling size; (b) calculating the input data values constituting the first unit with corresponding filter coefficients and sequentially outputting the number N times; (c) storing a part of the input data value of the previous block and relocating it to the current block so that the block of the input data value of the filter can be sequentially input; And (d) shifting the input data values one by one and repeatedly outputting the steps (a) and (b) L times.

In addition, an FIR filter according to an aspect of the present invention includes an input buffer for storing an input data block having a size of L; M multipliers that multiply the input data by a filter coefficient;

And an output unit configured to accumulate and output the multiplied value, wherein the input buffer rearranges the input data values so that zero padding is omitted.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

1 is a view showing the structure of a typical FIR filter.

With reference to FIG. 1, the filter of block size 128, filter tap size 48, and oversampling size 8 is demonstrated as an example.

As shown in Fig. 1, the filter has 128 input values In_data [] corresponding to indices of 0 to 127, and 48 filter coefficients coeff [] corresponding to indices of 0 to 47. A flip-flop that outputs an input value In-data [], a multiplier that multiplies the filter value coeff [] output from the flip-flop, and all the filter coefficients coeff [0] to [47] And an adder that sums all of the respective multiplying outputs with all corresponding inputs.

The shaping filter of the pulse has zero padding on the input value In-data [] for sharpness of the output pulse, for example, seven zero values as the input value of the filter according to the oversampling size 8. (0) is input, followed by one actual data value.

2 is a diagram for describing an operation of a filter using zero padding.

Hereinafter, a filter defined as a block size 128, a filter tab size 48, and an over sampling size 8 will be described as an example.

When the filter implementation on the DSP was mentioned above, it was mentioned that the input data is loaded in one block after receiving the input in block units instead of storing the input value in a register. It is assumed that there is a register that stores.

First, referring to (I) of FIG. 2, the pulse shaping filter of the transmitter performs seven zero paddings. That is, in the input value input to the filter register in units of oversampling size (8) in FIG. 2 (I), seven zero values (0) are input first, followed by one actual data value In_data [ 0]) is entered. Repeating this, as shown in Fig. 2I, input values In_data [0] to In_data [5] including zero padding are stored in the filter register corresponding to all the filter coefficients Filter_Coeff [].

Hereinafter, the filter operation for obtaining the output of the FIR filter according to an embodiment of the present invention is as follows.

In Fig. 2 (I), the calculation between the zero padded portion and the filter coefficient in the filter register is zero anyway, so the calculation is omitted. If only the values of registers with actual data values (In_data [0] to In_data [5]) are multiplied by the filter coefficients, the filter output value (filter_out [0]) is the data value (In_data [0]) and the filter coefficients (coeff). [40] first output (out0) multiplied by data value (In_data [1]) and second output (out1) multiplied by filter coefficient (coeff [32]), data value (In_data [2]) and filter The third output out2 multiplied by the coefficient coeff [24], the fourth output out3 multiplied by the data value In_data [3] and the filter coefficient coeff [16], and the data value In_data [4] ) And the fifth output (out4) multiplied by the filter coefficient (coeff [8]) and the sixth output (out5) multiplied by the data value (In_data [5]) and the filter coefficient (coeff [0]). filter_out [0]) can be obtained. As described above, in the filter according to the embodiment of the present invention, the calculation of the zero-padded input value is performed in a total of 48 filter calculations, including the calculation of the zero-padded input value to obtain the filter output (Filter_out [0]). Except, you only need to do 6 multiplications for the input values (In_data [0] ~ In_data [5]). Here, it can be seen that the sharpness of the output pulse can be guaranteed even if the number of multiplications required to obtain one output value in the zero padding environment in the filter according to the embodiment of the present invention is reduced to one eighth.

Next, in FIG. 2 (II), as shown in (I), the input value stored in the filter register in which the input values In_data [0] to [5] are stored, including the zero value, has one filter output ( filter_out []) is obtained and then shifted one by one. That is, seven zero values are input according to the oversampling size (8), one data value is input to the filter register until the first output is obtained from the filter, and the second output to the seventh output is obtained. This shift by one is repeated. In the filter according to the embodiment of the present invention, when seven zero values and one data value are repeatedly input in response to a total of 48 filter coefficients, six data values may be input at a time to obtain one output. A total of eight output values can be obtained corresponding to the data values In_data [0] to [5].

The operation of obtaining the filter output values filter_out [1] to filter_out [7] shown in (II) of FIG. 2 is the same as the filter operation described in (I) of FIG. Description is omitted.

Meanwhile, as described above, when the operation for calculating the filter outputs filter_out [0] to [7] ends, the calculation for the first input value In_data [0] ends and the new input value ( In_data [6]) is input and an operation for obtaining eight filter outputs corresponding to the input values [In_data [1] to [6]) is performed.

The filter operation is repeated until the operation of obtaining the filter output corresponding to all input values ends.

Accordingly, the filter according to the embodiment of the present invention may obtain a total of 1024 filter outputs corresponding to 128 input values In_data []. The calculation of the number of filter outputs can be expressed as the product of the number of inputs and the sampling size.

As described above, the calculation of the filter coefficient corresponding to the zero value input during the filter operation according to the embodiment of the present invention is omitted so that the number of multiplications for obtaining one filter output is one eighth, that is, 1 / over sampling. It can be seen that the size has been reduced.

In the embodiment of the present invention, in order to reduce the amount of calculation while using the feature of zero padding, the filtering process is performed only for a value obtained by dividing the tap size of the filter by the number of oversampling. That is, the input data values of the filter register or the buffer are shifted at intervals corresponding to the number of oversamplings OVER_SAMPLE, and by performing filtering continuously, the same effect as zero padding without additional calculation can be expected.

On the other hand, in order to use the soft pipeline which is a characteristic of the DSP during the filter operation according to the embodiment of the present invention, since the index of the filter coefficients must be changed regularly, the multiplication calculation is performed in response to the rearrangement of the filter coefficients or the filter coefficients. You need to rearrange the input (In_data []).

3 is a diagram illustrating rearranging filter coefficients according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating rearranging input values according to an embodiment of the present invention.

As shown in Fig. 3, Fig. 3 (a) shows the arrangement of the original filter coefficients, and (b) shows the arrangement of the rearranged filter coefficients.

The rearrangement of the filter coefficients is a sequence of filter coefficients multiplied by the values of the registers having the actual data values (In_data []), except for the zero values, in order corresponding to the original filter coefficients. Referring to Fig. 2 (I), the filter coefficient multiplied by the actual data value In_data [0] is Filter_Coeff [40]. Next, the filter coefficient multiplied by the data value In_data [1] is Filter_Coeff [32]. If this is repeated, all filter coefficients multiplied by the actual data values in Fig. 2 (I) are Filter_Coeff [40], [32], [24], [16], [8], and [0]. The same applies to (II) of FIG. 2 and rearranges the total of 48 filter coefficients multiplied with the actual data values corresponding to the original filter coefficients while obtaining eight outputs, as shown in FIG. same.

For example, in FIG. 3B, the rearranged filter coefficient Filter_Re_Coeff [0] is the filter coefficient Filter_Coeff [40], and the rearranged filter coefficient Filter_Re_Coeff [1] is the filter coefficient Filter_Coeff [. 32]), and the rearranged filter coefficients Filter_Re_Coeff [2] are filter coefficients Filter_Coeff [24]. When all of the rearrangement process is performed, the rearranged filter coefficients Filter_Re_Coeff [47] are the filter coefficients Filter_Coeff [7].

The rearrangement as described above is represented by an algorithm. The rearrangement of the filter coefficients only needs to be performed once during initialization of the filter, and thus does not affect the operation of the filter.

<Filter coefficient rearrangement algorithm>
for (k = 0; k <(OVER_SAMPLE); k ++)
{
for (l = 0; l <(FIR_TAB_SIZE / OVER_SAMPLE); l ++)
{
re_coeff [(FIR_TAB_SIZE / OVER_SAMPLE) * k + l] =
coeff [OVER_SAMPLE * (l + 1) -1-k];
}
}

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On the other hand, in the implementation of the filter on the DSP, the input of the filter is processed in units of blocks instead of one input, and the output value of the filter is directly obtained by using input values and coefficients in units of blocks. Therefore, for the filter operation in the current block in the filter operation processed in units of blocks with respect to the sequential filter input values in which the input and the output occur in succession, the last data of the previous block must be referenced. Therefore, it is necessary to rearrange the input values of the filter so that the data of the previous block can be referenced from the input values of the current filter.

Referring to FIG. 4, (a) shows that filter input values of the current block (nth block) are arranged, and (b) shows a filter rearranged to refer to a part of data of the previous block (n-1 block). It shows the input value.

The number of references to the data of the previous block may be arbitrarily determined. In the filter according to the exemplary embodiment of the present invention, the filter tap size 48 is divided by the oversampling size 8 from the end of the previous block. The number is placed above the input value (in_data []) of the current block. Therefore, in order to rearrange the input values according to an embodiment of the present invention, referring to (b) of FIG. 4, 5 (tap size 48 / oversampling size (8) -1) of the data values of the previous block are determined. This is done by arranging on top of the input values of the current block. Detailed description thereof is as follows.

As shown in (b) of FIG. 4, the rearranged input value Re_In_data [] is sequentially converted from the previous block data (In_data [123]) to (In_data) from the rearranged input value Re_In_data [0]. [127]) is arranged, and the data of the current block ((In_data [0]) to (In_data [127])) is arranged in succession. The rearrangement of the input values may be rearranged once every block unit calculation.

5 is a view showing the structure of a pulse shaping FIR filter according to an embodiment of the present invention. 5 shows an optimized pulse shaping FIR filter structure in consideration of all the features and rearrangements described above.

Referring to FIG. 5, in a filter having a filter tap size 48, an oversampling size 8, and the number of input values 128, seven zero values are input according to the oversampling size 8, and 1 Data values are input and multiplied by the number of all filter coefficients to obtain one output, the multiplication of the filter coefficients with zero values is ignored and the actual data values and the calculated filter coefficients are rearranged in order. By multiplying the rearranged input values (Re_In_data []) corresponding to the filter coefficients (Filter_Re_Coeff []), it can be seen that the number of filter multiplications for obtaining one output can be reduced to one eighth. .

In more detail, in order to obtain one output in FIG. 2, the filter values corresponding to the actual data values are collected and processed in units of blocks corresponding to the rearranged filter coefficients. By multiplying the rearranged input values with respect to, it can be seen that a total of eight filter outputs can be obtained corresponding to the rearranged filter coefficients Filter_Re_Coeff [].

Thus, a total of 1024 filter outputs are obtained by repeating obtaining eight outputs corresponding to the filter coefficients arranged once from [0] to [47] until the last filter output is obtained.

Hereinafter, an algorithm for describing an optimized pulse shaping FIR filter structure according to an embodiment of the present invention is as follows.

FIR filter operation algorithm according to an embodiment of the present invention
for (i = 0; i <BLOCK_SIZE; i ++)
{
for (j = 0; j <OVER_SAMPLE; j ++)
{
filter_out [i * OVER_SAMPLE + j] = 0;
for (h = 0; h <(FIR_TAB_SIZE / OVER_SAMPLE); h ++)
{
filter_out [i * OVER_SAMPLE + j] + =
(in_data [i + h] * re_coeff [(j * (FIR_TAB_SIZE / OVER_SAMPLE)) + h]);
}
}
}

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As described above, according to the filtering method according to the embodiment of the present invention, the number of multiplications is 1 / over sample size (8) than when using the existing filter structure to obtain one filter output filter_out []. You can see that it reduced by). In other words, it can be seen that the DSP load is reduced by twice the oversampling size than when using the conventional filter structure.

In addition, using the filter structure according to the present invention, for example, when implemented in a DSP chip of 600 MHz (TI TMS320C6416) is implemented with 18% load, other processing (for example, digital It can be seen that the filter can be implemented together with the transmitter in the communication.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the filtering method of the pulse shaping FIR filter that can be implemented on the DSP chip according to the present invention, the use of the zero-padding feature while ignoring the calculation of the zero-padded value reduces unnecessary filter operations and obtains the multiplication necessary to obtain one filter output value. Optimizing performance at filter run time can be achieved by minimizing filter operations to reduce the number by 1 / over sampling size.

Claims (12)

delete A method of implementing a FIR filter having L input block sizes, M filter taps, and N oversampling sizes on a DSP, (a) repeatedly rearranging the input data values of the filter N times in a first unit corresponding to a value (M / N) obtained by dividing the number of filter taps by the oversampling size to omit a zero padding operation; (b) calculating the input data values constituting the first unit with corresponding filter coefficients and sequentially outputting the number N times; (c) rearranging the filter coefficients so that the input data values of the first unit can be sequentially input; And (d) shifting the input data values one by one and repeatedly outputting steps (a) and (b) L times; FIR filter implementation method comprising a. A method of implementing a FIR filter having L input block sizes, M filter taps, and N oversampling sizes on a DSP, (a) repeatedly rearranging the input data values of the filter N times in a first unit corresponding to a value (M / N) obtained by dividing the number of filter taps by the oversampling size to omit a zero padding operation; (b) calculating the input data values constituting the first unit with corresponding filter coefficients and sequentially outputting the number N times; (c) storing a part of the input data value of the previous block and relocating it to the current block so that the block of the input data value of the filter can be sequentially input; And (d) shifting the input data values one by one and repeatedly outputting steps (a) and (b) L times; FIR filter implementation method comprising a. The method of claim 2, The rearranging of the filter coefficients may include rearranging only the filter coefficients corresponding to the data values for performing the actual operation for each first unit, except for zero-padded values among the input data values of the filter. How to implement a FIR filter. The method of claim 3, And an input data value of a current block is rearranged such that (M / N-1) of input data values of a previous block are included in the first unit. The method of claim 4, wherein And the index of the rearranged filter coefficients decreases by the oversampling number in the filter coefficient index corresponding to the first input data. The method of claim 4, wherein The rearrangement of the filter coefficients only needs to be performed once at the time of the filter operation, and the number of filter coefficients is equal to the number of filter taps. In an FIR filter having an oversampling size of N implemented on a DSP, An input buffer for storing an input data block of size L; M multipliers that multiply the input data by a filter coefficient; An output unit accumulating and outputting the multiplied value; And the input buffer rearranges the input data values such that the input data values are zero padded. The method of claim 8, And the input buffer repeatedly rearranges the input data of the filter by the first unit corresponding to a value (M / N) obtained by dividing the number of multipliers by the oversampling size. The method of claim 9, The output unit, the FIR filter to calculate the input data value constituting the first unit with the corresponding filter coefficients and sequentially output N times. The method of claim 10, Input data is sequentially input to the input buffer, The multiplier includes a filter coefficient corresponding to a data value for performing an actual operation except for a zero-padded value among input data values of the filter. The method of claim 10, An input data block is continuously input to the input buffer, and an input data value of a current block is input so that (M / N-1) of input data values of a previous block are included in the first unit.

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