KR970013680A - Finite Shock Response (FIR) Filter Circuit Considering Low Power Consumption - Google Patents

Abstract

The present invention performs a multiplication operation between respective delay data and multiplication coefficients output from several delay elements connected in series to a digital input signal in advance before data processing using a preamplifier, thereby making it easier to use than other multipliers. The present invention relates to a FIR filter circuit considering low power consumption that can configure a circuit and reduce power consumption. A characteristic configuration includes all of the multiplication coefficients that satisfy a multiplier using a simple input signal having a difficult level value. Preamp means for performing multiplication calculation on the combination beforehand and processing the data and holding it at the output terminal, and level detection which detects the digital input signal to be processed as a simple input signal having various level values by dividing it into an arbitrary threshold value. And serially connected to the simple input signal of the level detecting means, respectively. Two delay means for obtaining the simple delay signal, and data for outputting one of all combination values of the multiplication coefficients held at the output of the preamplifier means by separating the delayed signal of the delay means one by one. And a separating means, and an adding means for obtaining one output signal by adding together the digital input signal to be processed and the separating signal of the data separating means.

Description

Finite Shock Response (FIR) Filter Circuit Considering Low Power Consumption

Since this is an open matter, no full text was included.

2 is a block diagram showing an embodiment of a three-tap FIR filter circuit according to the present invention.

3 is a reference table showing a combined signal between multiplication coefficients of a preamplifier circuit section set for a simple delay signal according to the present invention.

Claims (3)

Preamplifier means for performing multiplication calculation for all combinations of multiplication coefficients satisfying a multiplier beforehand by using a simple input signal having various level values and holding them in the output terminal; Level detecting means for dividing the digital input signal to be processed by an arbitrary threshold value and detecting the digital input signal as a simple input signal having various level values; Two delay means connected in series with the simple input signal of the level detecting means to generate respective delay signals; Data separation means for outputting one of all combination values of the multiplication coefficients held at the output of the preamplifier means to be matched to the current simple delay signal by outputting the separated delay signal one by one to the value of the delay signal; And an adding means for adding one of the digital input signals to be processed and the separating signals of the data separating means to obtain one output signal. 2. The FIR filter circuit according to claim 1, wherein the level detecting unit comprises a three level detecting unit which replaces the digital input signal to be processed with a simple input signal having a three level value. The FIR filter circuit according to claim 1, wherein the level detecting unit comprises a five level detection unit which replaces the digital input signal to be processed with a simple input signal having a five level value. ※ Note: The disclosure is based on the initial application.