KR960026388A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR960026388A
KR960026388A KR1019940034735A KR19940034735A KR960026388A KR 960026388 A KR960026388 A KR 960026388A KR 1019940034735 A KR1019940034735 A KR 1019940034735A KR 19940034735 A KR19940034735 A KR 19940034735A KR 960026388 A KR960026388 A KR 960026388A
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KR
South Korea
Prior art keywords
metal film
forming
metal wiring
semiconductor device
collimator
Prior art date
Application number
KR1019940034735A
Other languages
Korean (ko)
Other versions
KR0137565B1 (en
Inventor
김헌도
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940034735A priority Critical patent/KR0137565B1/en
Publication of KR960026388A publication Critical patent/KR960026388A/en
Application granted granted Critical
Publication of KR0137565B1 publication Critical patent/KR0137565B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 소정단차를 갖는 금속배선 형성부위에 제 1 금속막(23)을 형성하되, 콜리메이터를 이용하여 예정된 두께로 증착하는 제 1 단계; 상기 제 1 금속막 상부에 제 2 금속막을 형성하되,콜리메이터를 이용하여 예정된 두께의 일부(24)만을 중착하는 제 2 단계; 제 2 금속막의 나머지 두께를 콜리메이터를 이용하지 않고 증착(26)하는 제 3 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising: forming a first metal film (23) on a metal wiring forming portion having a predetermined step, using a collimator to deposit a predetermined thickness; A second step of forming a second metal film on the first metal film, and neutralizing only a portion 24 of a predetermined thickness by using a collimator; And a third step of depositing (26) the remaining thickness of the second metal film without using a collimator.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 본 발명에 따라 금속배선 하부의 확산방지막 형성후의 단면도, 제 3A 도 내지 제 3C 도는 본 발명에 따른 금속배선 형성 공정 단면도.2 is a cross-sectional view after the diffusion barrier film is formed in the lower portion of the metal wiring in accordance with the present invention, 3A to 3C is a cross-sectional view of the metal wiring forming process according to the present invention.

Claims (3)

반도체 소자의 금속배선 형성방법에 있어서, 소정단차를 갖는 금속배선 형성부위에 제 1 금속막을 형성하되, 콜리메이터를 이용하여 예정된 두께로 증착하는 제 1 단계; 상기 제 1 금속막 상부에 제 2 금속막을 형성하되, 콜리메이터를 이용하여 예정된 두께의 일부만을 증착하는 제 2 단계; 제 2 금속막의 나머지 두께를 콜리메이터를 이용하지 않고 증착하는 제 3 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Claims [1] A method of forming a metal wiring in a semiconductor device, the method comprising: forming a first metal film on a metal wiring forming portion having a predetermined step, and depositing a predetermined thickness by using a collimator; Forming a second metal film on the first metal film, and depositing only a portion of a predetermined thickness by using a collimator; And depositing the remaining thickness of the second metal film without using a collimator. 제 1 항에 있어서, 상기 제 3 단계 공정후 금속막을 증착하여 단차부위를 매립하는 제 4 단계; 상기 금속막 상부에 반사방지막을 형성하는 제 5 단계를 더 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, further comprising: filling a stepped portion by depositing a metal film after the third step process; And a fifth step of forming an anti-reflection film over the metal film. 제 1 항에 있어서, 상기 제 1 금속막은 티타늄막, 제 2 금속막은 티타늄나이트라이드막인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the first metal film is a titanium film, and the second metal film is a titanium nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940034735A 1994-12-16 1994-12-16 Method of fabrication metal in semiconductor device KR0137565B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940034735A KR0137565B1 (en) 1994-12-16 1994-12-16 Method of fabrication metal in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940034735A KR0137565B1 (en) 1994-12-16 1994-12-16 Method of fabrication metal in semiconductor device

Publications (2)

Publication Number Publication Date
KR960026388A true KR960026388A (en) 1996-07-22
KR0137565B1 KR0137565B1 (en) 1998-06-01

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ID=19401941

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940034735A KR0137565B1 (en) 1994-12-16 1994-12-16 Method of fabrication metal in semiconductor device

Country Status (1)

Country Link
KR (1) KR0137565B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480913B1 (en) * 2002-06-28 2005-04-07 주식회사 하이닉스반도체 Method for burying contact using stacked Ti/TiN

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480913B1 (en) * 2002-06-28 2005-04-07 주식회사 하이닉스반도체 Method for burying contact using stacked Ti/TiN

Also Published As

Publication number Publication date
KR0137565B1 (en) 1998-06-01

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