KR950004499A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR950004499A
KR950004499A KR1019930013479A KR930013479A KR950004499A KR 950004499 A KR950004499 A KR 950004499A KR 1019930013479 A KR1019930013479 A KR 1019930013479A KR 930013479 A KR930013479 A KR 930013479A KR 950004499 A KR950004499 A KR 950004499A
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South Korea
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layer
tin
forming
cvd
semiconductor device
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KR1019930013479A
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Korean (ko)
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KR970003717B1 (en
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이경일
주승기
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 고집적 반도체 장치의 금속배선 형성방법에 관한것으로, 종래 Al을 이용한 콘택플러그 형성시의 표면토플로지가 좋지 않고 일렉트로 마이그레이션에 약한 문제를 해결하기 위하여 콘택개구부내에 배리어층을 증착한후, CVD Al층과 Cu층 및 CVD Al층을 차례로 형성한 콘택플러그를 형성하는 방법을 제공하며, 또한 콘택개구부내에 배리어층 TiN용 Al핵생성 촉진용 TiN층으로 된 이중 TiN층을 형성한 후, CVD Al층을 증착하여 콘택플러그를 형성하는 방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a highly integrated semiconductor device. In order to solve the problem of poor surface topography and weak electro migration during the formation of a contact plug using Al, a CVD layer is deposited in the contact opening. Provided is a method for forming a contact plug in which an Al layer, a Cu layer, and a CVD Al layer are sequentially formed, and a double TiN layer of an Al nucleation promoting TiN layer for barrier layer TiN is formed in the contact opening, and then CVD Al is formed. A method of forming a contact plug by depositing a layer is provided.

Description

반도체 장치의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 제1실시예에 따른 콘택플러그 형성방법을 나타낸 공정순서도. 제5도는 본 발명의 제2실시예에 따른 콘택플러그 형성방법을 나타낸 공정순서도.4 is a process flowchart showing a method for forming a contact plug according to a first embodiment of the present invention. 5 is a process flowchart showing a contact plug forming method according to a second embodiment of the present invention.

Claims (11)

기판(1)상의 절연막(2)에 형성된 콘택개구부내에 배리어층(5)을 형성하는 공정과, 상기 배리어층(5)상에 제1 CVD Al층(10)을 소정두께로 형성하는 공정, 상기 제1CVD Al층(10)상에 Cu(11)을 증착하는 공정, 및 상기 Cu층(11)상에 제2 CVD Al층(12)을 형성하여 콘택개구부를 매몰시키는 공정을 구비한 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.Forming a barrier layer 5 in a contact opening formed in the insulating film 2 on the substrate 1, forming a first CVD Al layer 10 on the barrier layer 5 to a predetermined thickness, and And depositing Cu (11) on the first CVD Al layer (10), and forming a second CVD Al layer (12) on the Cu layer (11) to bury the contact openings. A metal wiring forming method of a semiconductor device. 제1항에 있어서, 상기 배리어층(5)은 TiN을 증착시켜 형성함을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 1, wherein the barrier layer (5) is formed by depositing TiN. 제1항에 있어서, 상기 제1 CVD Al층(10)은 상기 콘택개구부 직경이 1/2정도에 해당하는 두께로 형성함을 특징으로 하는반도체 장치의 금속배선 형성방법.2. The method of claim 1, wherein the first CVD Al layer (10) is formed to a thickness that corresponds to a diameter of the contact opening portion of about 1/2. 제1항에 있어서, 상기 Cu층(11)은 20∼50Å두께로 형성함을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 1, wherein the Cu layer (11) is formed to a thickness of 20 to 50 GPa. 제1항에 있어서, 상기 제2 CVD Al층(12)을 형성하는 공정후에 열처리하는 공정을 더 구비함을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 1, further comprising a step of heat treatment after the step of forming the second CVD Al layer (12). 기판(1)상의 절연막(2)상에 형성된 콘택개구부내에 제1 TiN층(5)을 형성하는 공정과, 상기 제1 TiN층(5)상에 제2 TiN(14)을 형성하고 연속적으로 장비의 진공을 유지하여 VD Al층(15)을 형성하는 공정을 구비함을 특징으로 하는 반도체 장치의금속배선 형성방법.Forming a first TiN layer 5 in a contact opening formed on the insulating film 2 on the substrate 1, and forming a second TiN 14 on the first TiN layer 5 and continuously And forming a VD Al layer (15) by maintaining a vacuum of the metal. 제6항에 있어서, 상기 제1 TiN층(5)은 TiN 증착 후 스터핑하여 형성하는 것임을 특징으로 하는 반도체 장치의 금속배선 형성방법.7. The method of claim 6, wherein the first TiN layer (5) is formed by stuffing after TiN deposition. 제7항에 있어서, 상기 제1 TiN층(5)을 300∼500Å 두께로 형성함을 특징으로 하는 반도체 장치의 금속배선 형성방법.8. The method of claim 7, wherein the first TiN layer (5) is formed to a thickness of 300 to 500 kHz. 제6항에 있어서, 상기 제2 TiN층(14) 및 CVD Al층(15)을 연속적으로 형성하는 공정은 TiN층(14)을 증착한후 장비의 진공상태를 유지하여 스퍼터링하지 않고 연속적으로 CVD Al을 증착하는 것임을 특징으로 하는 반도체 장치의 금속배선 형성방법.7. The process of claim 6, wherein the second TiN layer 14 and the CVD Al layer 15 are continuously formed without depositing the TiN layer 14 and maintaining the vacuum state of the equipment. The metal wiring forming method of a semiconductor device, characterized in that to deposit Al. 제6항에 있어서, 상기 제2 TiN층(14)은 50∼100Å 정도의 두께로 형성함을 특징으로 하는 반도체 장치의 금속배선 형성방법.7. The method of claim 6, wherein the second TiN layer (14) is formed to a thickness of about 50 to 100 GPa. 제6항에 있어서, 상기 CVD Al층(15)을 형성하여 콘택개구부를 매몰시키는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.7. The method of claim 6, wherein the CVD Al layer (15) is formed to bury the contact openings. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930013479A 1993-07-16 1993-07-16 Method of forming the metal wiring on the semiconductor device KR970003717B1 (en)

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KR101043992B1 (en) 2004-08-12 2011-06-24 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating thereof
KR101037322B1 (en) 2004-08-13 2011-05-27 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating thereof
KR101048903B1 (en) 2004-08-26 2011-07-12 엘지디스플레이 주식회사 LCD and its manufacturing method
KR101050899B1 (en) 2004-09-09 2011-07-20 엘지디스플레이 주식회사 LCD and its manufacturing method
KR101078360B1 (en) 2004-11-12 2011-10-31 엘지디스플레이 주식회사 Liquid Crystal Display Panel of Poly-type and Method of Fabricating The Same
KR101153297B1 (en) 2004-12-22 2012-06-07 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating the same
KR101086487B1 (en) 2004-12-24 2011-11-25 엘지디스플레이 주식회사 Poly Thin Film Transistor Substrate and Method of Fabricating The Same
KR101107252B1 (en) 2004-12-31 2012-01-19 엘지디스플레이 주식회사 Thin film transistor substrate in electro-luminescence dispaly panel and method of fabricating the same
KR101125252B1 (en) 2004-12-31 2012-03-21 엘지디스플레이 주식회사 Poly Liquid Crystal Dispaly Panel and Method of Fabricating The Same
KR101107251B1 (en) 2004-12-31 2012-01-19 엘지디스플레이 주식회사 Poly Thin Film Transistor Substrate and Method of Fabricating The Same

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