KR960026238A - Method for forming contact portion during metal wiring of semiconductor device and its structure - Google Patents

Method for forming contact portion during metal wiring of semiconductor device and its structure Download PDF

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KR960026238A
KR960026238A KR1019940039573A KR19940039573A KR960026238A KR 960026238 A KR960026238 A KR 960026238A KR 1019940039573 A KR1019940039573 A KR 1019940039573A KR 19940039573 A KR19940039573 A KR 19940039573A KR 960026238 A KR960026238 A KR 960026238A
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contact portion
contact
layer
substrate
buried
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KR1019940039573A
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KR100325469B1 (en
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신봉조
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문정환
Lg 반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명에 의한 반도체장치의 금속배선시 콘택부 형성방법은 반도체소자의 각 구성요소를 형성시킨 반도체 기판 전면에 제1절연층을 형성시키고, 그 전면에 매몰 콘택부위를 개방하는 포토레지스트패턴를 형성시킨 후에, 포토레지스트패턴을 마스크로 제1절연층을 식각제거하여 매몰콘택부위의 기판 표면을 노출시키는 단계와, 포토레지스트패턴을 제거한 후에, 매몰콘택부를 덮는 도전형물질의 패드층을 중앙부위는 메몰콘택부위의 기판 표면과 접하고, 가장자리 부위는 메몰콘택부위 가장자리의 제1절연층 표면과 접하는 요철형태로 형성시키고 매몰콘택부위의 기판표면에 패드층과 접촉되는 고농도불순물영역을 형성시키는 단계와, 메몰콘택부위의 고농도불순물영역에 접촉하면서, 매몰콘택부위를 덮는 패드층을 형성시킨 기판 전면에 제2절연층을 형성시키는 단계와, 패드층의 콘택부위 위의 제2절연층을 식각제거하여 패드층의 콘택부의를 노출시킨 후에, 금속을 증착시키고, 콘택부위 이외의 금속을 사진식각하여 패드층의 콘택부위와 접촉하는 금속배선을 형성시키는 단계를 포함하여 이루어지며, 그 구조는 반도체 기판 표면의 제1절연층의 일부가 개방되어 형성되어진 메몰콘택부위와, 메몰콘택부위를 덮으면서 형성된 도전형 물질의 패드층을 통하여 불순물이온이 자동도핑되어 상기 패드층과 접촉되면서 메몰콘택부위의 기판표면에 형성되어진 고농도불순물영역과, 패드층표면의 제2절연층의 일부가 개방되어 형성되어진 콘택영역에서 패드층과 접촉하며 형성된 금속배선을 포함하여 이루어진다.In the method of forming a contact portion during metal wiring of a semiconductor device according to the present invention, a first insulating layer is formed on an entire surface of a semiconductor substrate on which each component of the semiconductor element is formed, and a photoresist pattern is formed on the entire surface of the semiconductor substrate to open a buried contact portion. Subsequently, the first insulating layer is etched away using the photoresist pattern as a mask to expose the substrate surface of the buried contact portion, and after the photoresist pattern is removed, the pad layer of the conductive material covering the buried contact portion is buried in the center portion. Forming a high concentration impurity region in contact with the substrate surface of the contact portion, the edge portion having an uneven shape in contact with the surface of the first insulating layer at the edge of the buried contact region, and contacting the pad layer on the substrate surface of the investment contact portion; Second insulation on the entire surface of the substrate on which the pad layer covering the buried contact portion is formed while contacting the high concentration impurity region of the contact portion. And etching the second insulating layer over the contact portion of the pad layer to expose the contact portion of the pad layer, depositing a metal, and etching the metal other than the contact portion to photo-etch the contact portion of the pad layer. And forming a metal wiring in contact with the pad, wherein the structure is formed of a buried contact portion formed by opening a portion of the first insulating layer on the surface of the semiconductor substrate, and a pad of a conductive material formed by covering the buried contact portion. The impurity ions are automatically doped through the layer to contact the pad layer, and the high concentration impurity region formed on the substrate surface of the buried contact portion and the contact region formed by opening a part of the second insulating layer on the surface of the pad layer. It comprises a metal wiring formed in contact.

Description

반도체장치의 금속배선시 콘택부 형성방법 및 그 구조.Method and method for forming contact portion during metal wiring of semiconductor device.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 반도체장치의 금속배선시 콘택부를 설명하기 위한 도면으로, 제2도의 (가)에서 (라)도는 본 발명에 의한 반도체장치의 금속배선시 콘택부의 형성단계를 도시한 단면을 도신한 도면, 제2도의 (마)는 본 발명의 방법에 의해 형성된 반도체장치의 금속배선시 콘택부의 실시예로 마스크롬의 콘택부 평면도를 도시한 도면.2 is a view for explaining the contact portion during the metal wiring of the semiconductor device according to the present invention, Figure 2 (a) to (d) is a cross-sectional view showing the step of forming a contact portion during the metal wiring of the semiconductor device according to the present invention. Is a plan view of a contact portion of a mask rom as an embodiment of a contact portion during metal wiring of a semiconductor device formed by the method of the present invention.

Claims (6)

반도체장치의 금속배선시 콘택부 형성방법에 있어서, 1) 반도체 소자의 각 구성요소를 형성시킨 반도체 기판 전면에 제1절연층을 형성시키고. 그 전면에 매몰 콘택부위를 개방하는 포토레지스트패턴를 형성시킨 후에, 포토레지스트패턴을 마스크로 상기 제1절연층을 식각제거하여 매몰콘택부위의 기판 표면을 노출시키는 단계와, 2) 상기 포토레지스트패턴을 제거한 후에, 상기 메몰콘택부위를 덮는 도전형물질의 패드층을 중앙부위는 상기 메몰콘택부위의 기판 표면과 접하고, 가장자리부위는 상기 메몰콘택부위 가장자리의 제 1절연층 표면과 접하는 요철형태로 형성시키고, 상기 메몰콘택부위의 기판표면에 상기 패드층과 접촉되는 고농도불순물영역을 형성시키는 단계와, 3) 상기 메몰콘택부위의 고농도불순물영역에 접촉하면서, 매몰콘택부위를 덮는 상기 패드층을 형성시킨 기판 전면에 제2절연층을 형성시키는 단계와, 4) 상기 패드층의 콘택부위 위의 제2절연층을 식각제거하여 상기 패드층의 콘택부위를 노출시킨 후에, 금속을 증착시키고,콘택부위 이외의 금속을 사진식각하여 상기 패드층의 콘택부위와 접촉하는 금속배선을 형성시키는 단계를 포함하는 반도체장치의 금속배선시 콘택부 형성방법.A method of forming a contact portion during metal wiring of a semiconductor device, comprising: 1) forming a first insulating layer on the entire surface of a semiconductor substrate on which each component of the semiconductor element is formed. Forming a photoresist pattern on the entire surface of the buried contact portion, and then etching the first insulating layer with the photoresist pattern as a mask to expose the substrate surface on the buried contact portion; and 2) removing the photoresist pattern. After the removal, the pad layer of the conductive material covering the buried contact portion is formed in a concave-convex shape in which the center portion is in contact with the surface of the substrate of the buried contact portion, and the edge portion is in contact with the surface of the first insulating layer at the edge of the buried contact portion. Forming a high concentration impurity region in contact with the pad layer on the surface of the buried contact portion, and 3) a substrate having the pad layer covering the investment contact portion while contacting the high concentration impurity region in the buried contact region. Forming a second insulating layer on the front surface; and 4) etching away the second insulating layer on the contact portion of the pad layer. After exposing the contact portion of the drain layer, depositing a metal, and forming a metal wiring in contact with the contact portion of the pad layer by photo-etching metal other than the contact portion to form a contact portion during metal wiring of the semiconductor device. Way. 제1항에 있어서, 상기 2)단계에서 상기 도전형물질인 폴리실리콘이나 폴리사이드로 상기 메몰콘택부위를 덮는 패드층을 형성시키고, 상기 기판과 반대도전형의 고농도불순물을 이온주입시키면, 불순물이온이 상기 패드층을 통하여 메몰콘택부위의 기판내부로 자동도핑되어서, 상기 패드층과 접촉되는 고농도불순물영역이 상기 메몰콘택부위의 기판표면에 형성되는 것을 특징으로 하는 반도체장치의 금속배선시 콘택부 형성방법.The method of claim 1, wherein in the step 2) by forming a pad layer covering the molten contact portion with the polysilicon or polyside as the conductive material, and ion implanted a high concentration impurity of the opposite conductivity to the substrate, impurity ion The contact portion is formed during the metal wiring of the semiconductor device, characterized in that the doped impurity region is automatically doped into the substrate of the buried contact portion through the pad layer, so that a high concentration impurity region in contact with the pad layer is formed on the substrate surface of the buried contact portion. Way. 제2항에 있어서, 상기 2)단계에서 P형 기판인 경우에 POCl3에서 생성된 고농도의 N형 불순물인 인(P) 이온이 상기 패드층을 통하여 상기 매몰콘택부위의 기판 기판내부로 자동도핑되어서, 상기 패드층과 접촉되는 인(P) 이온의 고농도불순물영역이 상기 메몰콘택부위의 기판표면에 형성되는 것을 특징으로 하는 반도체장치의 금속배선시 콘택부 형성방법.The method of claim 2, wherein in the case of the P-type substrate in step 2), phosphorus (P) ions, which are high concentration N-type impurities generated in POCl 3 , are automatically doped into the substrate substrate of the buried contact region through the pad layer. And a high concentration impurity region of phosphorus (P) ions in contact with the pad layer is formed on the surface of the substrate on the buried contact portion. 제1항에 있어서, 상기 제1절연층으로 제1산화막을 형성시키고, 상기 제2절연층으로 제2산화막과 제3산화막, BPSG를 순차적으로 적층하여 형성시키는 것을 특징으로 하는 반도체장치의 금속배선시 콘택부 형성방법.The metal wiring of claim 1, wherein a first oxide layer is formed of the first insulating layer, and a second oxide layer, a third oxide layer, and a BPSG are sequentially stacked on the second insulating layer. Method of forming contact portion at the time. 반도체장치의 금속배선시 콘택부 구조에 있어서, 반도체 기판 표면의 제1절연층의 일부가 개방되어 형성되어진 메몰콘택부위와, 상기 메몰콘택부위를 덮으면서 형성된 도전형 물질의 패드층과, 상기 패드층을 통하여 불순물이온이 자동도핑되어 상기 패드층과 접촉되면서 상기 매몰콘택부위의 기판표면에 형성되어진 고농도불순물영역과, 상기 패드층표면의 제2절연층의 일부가 개방되어 형성되진 콘택영역에서 패드층과 접촉하며 형성된 금속배선을 포함하여 이루어진 반도체장치의 금속배선시 콘택부 구조.In the contact structure of the metal device of the semiconductor device, a contact portion formed by opening a portion of the first insulating layer on the surface of the semiconductor substrate, a pad layer of a conductive material formed while covering the contact portion, and the pad The impurity ions are automatically doped through the layer to contact the pad layer, so that a high concentration impurity region is formed on the substrate surface on the buried contact portion, and a part of the second insulating layer on the surface of the pad layer is opened. A structure of a contact portion during metallization of a semiconductor device including a metallization formed in contact with a layer. 제5항에 있어서, 상기 패드층은 중앙부위가 상기 메몰콘택부위의 기판 표면과 접하고, 가장자리부위가 상기 메몰콘택부위 가장자리의 제1절연층의 표면과 접하는 요철형태로 형성된 것을 특징으로 하는 반도체장치의 금속배선시 콘택부 구조.6. The semiconductor device according to claim 5, wherein the pad layer is formed in a concave-convex shape in which a center portion is in contact with the surface of the substrate of the buried contact portion and an edge portion is in contact with the surface of the first insulating layer at the edge of the buried contact portion. Structure of the contact part when wiring metal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039573A 1994-12-30 1994-12-30 Method for forming contact part for metallization in semiconductor device and structure thereof KR100325469B1 (en)

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KR100325469B1 KR100325469B1 (en) 2002-07-31

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