KR960019681A - Semiconductor device with non-rectangle semiconductor chip - Google Patents

Semiconductor device with non-rectangle semiconductor chip Download PDF

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Publication number
KR960019681A
KR960019681A KR1019950038845A KR19950038845A KR960019681A KR 960019681 A KR960019681 A KR 960019681A KR 1019950038845 A KR1019950038845 A KR 1019950038845A KR 19950038845 A KR19950038845 A KR 19950038845A KR 960019681 A KR960019681 A KR 960019681A
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lead
semiconductor chip
pads
integrated circuit
semiconductor
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KR1019950038845A
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Korean (ko)
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KR100255180B1 (en
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히로시 사이토
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우에시마 세이스케
야마하 가부시키가이샤
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Publication of KR960019681A publication Critical patent/KR960019681A/en
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Publication of KR100255180B1 publication Critical patent/KR100255180B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

LSI 칩의 형상은 6각형으로 이루어지며, 이 칩은 6각 또는 원형스테이지에 접착되며, 다수의 인너리드가 본딩와이어에 의해 칩상의 패드중 해당 패드에 접속되며, 상기 칩의 형상이 원형에 가까우므로 접착제가 칩코너에 충분히 확산되며, 열적 스트레스가 완화될 수 있다. 리드프레임은 상기 리드의 인너리드의 선단부를 결합하는 라인을 이루도록 형성되어 칩사이즈의 임의의 변경을 용이하게 한다.The shape of the LSI chip is hexagonal, and the chip is bonded to the hexagonal or circular stage, and a plurality of inner leads are connected to the corresponding pads of the pads on the chip by bonding wires, and the shape of the chip is almost circular. Therefore, the adhesive is sufficiently diffused in the chip corner and thermal stress can be alleviated. The leadframe is formed to form a line that joins the leading end of the inner lead of the lead to facilitate any change in chip size.

Description

비 장방형 반도체 칩을 가진 반도체 장치Semiconductor device with non-rectangle semiconductor chip

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 일 실시예에 따른 LSI칩 형성 공정을 도시하는 웨이퍼의 상면도,1 is a top view of a wafer illustrating an LSI chip forming process according to an embodiment of the present invention;

제2도는 LSI칩을 확대하여 도시한 상면도,2 is a top view showing an enlarged LSI chip;

제3도는 LSI칩의 패키지 수납상태를 도시하는 상면도.3 is a top view showing a package storage state of the LSI chip.

Claims (10)

집적회로를 내장하며, 6각형 이상의 다각형으로된 반도체칩; 및 상기 반도체 칩을 접착한 지지스테이지를 구비하는 것을 특징으로 하는 반도체장치.A semiconductor chip having an integrated circuit and formed of a hexagonal polygon or more; And a support stage to which the semiconductor chip is bonded. 제1항에 있어서, 상기 다각형은 정육각형인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the polygon is a regular hexagon. 제1항에 있어서, 상기 다각형이 복수의 6각형을 접속한 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the polygons connect a plurality of hexagons. 집적회로를 내장하고, 그 집적회로에 접속되며, 연부를 따라 배치된 다수의 패드를 가진 반도체 칩과, 상기 반도체 칩을 접착하는 지지스테이지와, 상기 반도체의 주변부에 배치되며, 각기 인너리드와 아우더리드를 가진 다수의 리드와, 상기 반도체칩, 상기 지지스테이지 및 상기 리드의 인너리드를 수납하는 수지몰드를 구비하고, 상기 반도체 칩은 6이상의 다각형이며, 상기 리드의 인너리드는 다수의 패드에 각기 전기접속되며 상기 리드의 아우더리드는 수지몰드의 외측으로 연장된 것을 특징으로 하는 반도체장치.A semiconductor chip having an integrated circuit and connected to the integrated circuit, the semiconductor chip having a plurality of pads disposed along an edge thereof, a support stage for adhering the semiconductor chip, and disposed at a periphery of the semiconductor, each of an inner lead and an outer ring; A plurality of leads having a lead, and a resin mold for accommodating the semiconductor chip, the support stage and the inner lead of the lead, wherein the semiconductor chip is six or more polygons, and the inner lead of the lead is formed on a plurality of pads. And the outer lead of the lead extends to the outside of the resin mold, respectively. 제4항에 있어서, 상기 다수의 리드의 인너리드의 선단부는 가상원 상에 배치되는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 4, wherein the leading end of the inner lead of the plurality of leads is disposed on a virtual circle. 집적회로를 내장하고, 그 집적회로에 접속되며, 연부를 따라 배치된 다수의 패드를 가진 반도체 칩과, 상기 반도체칩을 접착하는 지지스테이지와, 상기 반도체의 주변부에 배치되며, 각기 인너리드와 아우더리드를 가진 다수의 리드와, 상기 반도체칩, 상기 지지스테이지 및 상기 리드의 인너리드를 수납하는 패키지를 구비하고, 상기 반도체 칩은 6이상의 다각형이며, 상기 다수의 패드는 6이상의 다각형 형상 또는 원형형상으로 배치되며, 상기 리드의 인너리드는 다수의 패드에 각기 전기접속되며, 상기 리드의 아우더리드는 패키지의 외측으로 연장하는 것을 특징으로 하는 반도체장치.A semiconductor chip having an integrated circuit and connected to the integrated circuit, the semiconductor chip having a plurality of pads disposed along an edge thereof, a support stage for adhering the semiconductor chip, and disposed at a periphery of the semiconductor, respectively, A plurality of leads having a lead, and a package for accommodating the semiconductor chip, the support stage, and the inner lead of the lead, wherein the semiconductor chip is six or more polygons, and the plurality of pads are six or more polygonal shapes or circles. Wherein the inner lead of the lead is electrically connected to a plurality of pads, and the lead of the lead extends to the outside of the package. 제6항에 있어서, 상기 다수의 리드의 인너리드의 선단부는 가상원 상에 배치되는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 6, wherein the leading end of the inner lead of the plurality of leads is disposed on a virtual circle. 상기 반도체칩의 형성이 6각이상의 다각형을 가지는 것을 특징으로 하는 집적회로를 내장한 반도체장치.And wherein the semiconductor chip has a polygonal shape with six or more angles. 집적회로를 내장하고, 상기 집적회로에 접속되며, 연부를 따라 배치된 다수의 패드를 가진 반도체칩에 있어서, 상기 반도체칩의 형상은 6이상의 다각형이며, 상기 다수의 패드는 6이상의 다각형 형상 또는 원형형상으로 배치되는 것을 특징으로 하는 반도체칩.A semiconductor chip having an integrated circuit, connected to the integrated circuit, and having a plurality of pads disposed along an edge thereof, wherein the shape of the semiconductor chip is six or more polygons, and the plurality of pads are six or more polygonal shapes or circles. A semiconductor chip, characterized in that arranged in the shape. 인너리드 및 아우더리드를 가지는 다수의 리드를 포함하는 리드프레임에 있어서, 상기 리드의 인너리드의 선단부는 가상원 상에 배치되는 것을 특징으로 하는 리드프레임.A lead frame comprising a plurality of leads having an inner lead and an outer lead, wherein the leading end of the inner lead of the lead is disposed on a virtual circle. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950038845A 1994-11-02 1995-10-31 Semiconductor device with non-rectangular chip KR100255180B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-293982 1994-11-02
JP6293982A JPH08138988A (en) 1994-11-02 1994-11-02 Semiconductor device

Publications (2)

Publication Number Publication Date
KR960019681A true KR960019681A (en) 1996-06-17
KR100255180B1 KR100255180B1 (en) 2000-05-01

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US9263374B2 (en) 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor

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