KR960019512A - Contact hole formation method of semiconductor device - Google Patents
Contact hole formation method of semiconductor device Download PDFInfo
- Publication number
- KR960019512A KR960019512A KR1019940028659A KR19940028659A KR960019512A KR 960019512 A KR960019512 A KR 960019512A KR 1019940028659 A KR1019940028659 A KR 1019940028659A KR 19940028659 A KR19940028659 A KR 19940028659A KR 960019512 A KR960019512 A KR 960019512A
- Authority
- KR
- South Korea
- Prior art keywords
- gate conductive
- impurity ion
- contact hole
- conductive layer
- semiconductor device
- Prior art date
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 기판 상에 게이트 전도막, 게이트 전도막 측벽의 스페이서 절연막, 불순물 이온주입영역이 기형성된 반도체 소자의 트랜지스터 구조 전체상부에 형성되어 있는 절연막의 소정부위를 식각하여 게이트 전도막 및 불순물 이온주입영역을 오픈시키는 반도체 소자의 콘택 홀 형성 방법에 있어서; 상기 절연막의 소정부위를 식각하여 게이트 전도막 및 불순물 이온주입영역의 소정부위를 동시에 오픈시키고 오픈 영역상에 드러난 게이트 전도막 측벽의 스페이서 절연막을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택 홀 형성 방법에 관한 것으로, 불순물 이온주입영역과 게이트 전극이 동시에 노출되는 콘택 홀 형성시 게이트 전극 측벽에 형성되어 있는 스페이서를 제거함으로써 충분한 설계여유를 확보하여 소자의 특성 및 수율을 향상시키는 효과가 있다.According to an embodiment of the present invention, a gate conductive layer and an impurity ion are etched by etching a predetermined portion of a gate conductive layer, a spacer insulating layer on a sidewall of the gate conductive layer, and an insulating layer formed over the entire transistor structure of a semiconductor device in which an impurity ion implantation region is formed. A method for forming a contact hole in a semiconductor device to open an injection region; Etching a predetermined portion of the insulating layer to simultaneously open a predetermined portion of the gate conductive layer and the impurity ion implantation region, and removing the spacer insulating layer on the sidewall of the gate conductive layer exposed on the open region. The present invention relates to a method for forming a contact hole, in which a spacer formed on a sidewall of a gate electrode is removed when forming a contact hole in which an impurity ion implantation region and a gate electrode are simultaneously exposed, thereby securing sufficient design margin and improving device characteristics and yield. have.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2A도 내지 제2E도는 본 발명의 일실시예에 따른 콘택 홀 형성 공정도.2A through 2E are contact hole forming process diagrams according to an embodiment of the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940028659A KR960019512A (en) | 1994-11-02 | 1994-11-02 | Contact hole formation method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940028659A KR960019512A (en) | 1994-11-02 | 1994-11-02 | Contact hole formation method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR960019512A true KR960019512A (en) | 1996-06-17 |
Family
ID=66687787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940028659A KR960019512A (en) | 1994-11-02 | 1994-11-02 | Contact hole formation method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960019512A (en) |
-
1994
- 1994-11-02 KR KR1019940028659A patent/KR960019512A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |