KR960011611A - Clock-Dupling Devices - Google Patents

Clock-Dupling Devices Download PDF

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Publication number
KR960011611A
KR960011611A KR1019940023505A KR19940023505A KR960011611A KR 960011611 A KR960011611 A KR 960011611A KR 1019940023505 A KR1019940023505 A KR 1019940023505A KR 19940023505 A KR19940023505 A KR 19940023505A KR 960011611 A KR960011611 A KR 960011611A
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KR
South Korea
Prior art keywords
signal
inverting
clock
clock signal
exclusive
Prior art date
Application number
KR1019940023505A
Other languages
Korean (ko)
Other versions
KR970000254B1 (en
Inventor
손영석
Original Assignee
배순훈
대우전자 주식회사
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Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019940023505A priority Critical patent/KR970000254B1/en
Publication of KR960011611A publication Critical patent/KR960011611A/en
Application granted granted Critical
Publication of KR970000254B1 publication Critical patent/KR970000254B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Abstract

본 발명은 아주 간단한 구조를 가지면서도 소자간의 시간지연을 이용함으로써, 입력되는 클럭신호보다 2배 빠른 주기를 갖는 클럭신호를 아주 용이하게 출력할 수 있는데, 기설정된 주기를 갖는 제1클럭신호(Fin)와 인버팅신호(I)를 입력받아, 배타 부정논리합(Exclusive NOR)연산하여, 제2클럭신호(Fout)를 출력하는 배타 부정논리합 수단(100)과, 인버팅신호(I)를 입력신호로 제공받고, 상기 배타 부정논리합 수단(100)으로부터 제공되는 제2클럭신호(Fout)에 응답하여, 상기 입력신호를 출력하는 D-플립플럽(120)과, 상기 D-플립플럽(120)으로부터 제공되는 신호를 인버팅(Inverting)하여, 인버팅신호(I)를 출력하는 인버팅 수단(140)을 포함한다.According to the present invention, a clock signal having a period twice as fast as an input clock signal can be easily outputted by using a time delay between elements while having a very simple structure. The first clock signal having a predetermined period (F) in ) and the inverting signal I, an exclusive NOR operation, and outputting the second clock signal F out and the exclusive negating logic means 100 and the inverting signal I. A D-flip flop 120 that is provided as an input signal and outputs the input signal in response to a second clock signal F out provided from the exclusive negative logic means 100, and the D-flip flop ( Inverting means (140) for inverting the signal provided from (120), and outputting the inverting signal (I).

Description

클럭-더블링 장치Clock-Dupling Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 클럭-더블링(Clock-Doubling)장치의 동작을 도식적으로 설명하기 위한 블럭도.1 is a block diagram for schematically illustrating the operation of a clock- doubling apparatus according to the present invention.

제2도는 본 발명에 따른 클럭-더블링 장치의 종작을 예시적으로 설명하기 위한 타이밍도.2 is a timing diagram for exemplarily illustrating the operation of the clock-dubbing device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

100 : EX-NOR 게이트 120 : D-플립플럽100: EX-NOR gate 120: D-flip flop

140 : 인버터140: inverter

Claims (1)

기설정된 주기를 갖는 제1클럭신호(Fin)와 인버팅신호(I)를 입력받아, 배타 부정논리합(Exclusive NOR) 연산하여, 제2클럭신호(Fout)를 출력하는 배타 부정논리합 수단(100)과 ; 인버팅신호(I)를 입력신호로 제공받고, 상기 배타 부정논리합 수단(100)으로부터 제공되는 제2클럭신호(Fout)에 응답하여, 상기 입력신호를 출력하는 D-플립플롭(120)과 ; 상기 D-플립플롭(120)으로부터 제공되는 신호를 인버팅(Inverting)하여, 인버팅신호(I)를 출력하는 인버팅 수단(140)을 포함하는 것을 특징으로 하는 클럭-더블링(Clock-Doubling) 장치.Exclusive negative logic means 100 for receiving a first clock signal Fin and an inverting signal I having a predetermined period, performing an exclusive NOR operation, and outputting a second clock signal F out . ) And; A D-flip flop 120 which receives the inverting signal I as an input signal and outputs the input signal in response to a second clock signal F out provided from the exclusive negative logic means 100; ; Clock-Doubling, characterized in that it comprises an inverting means 140 for inverting the signal provided from the D-flip-flop 120 and outputting the inverting signal I. Device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940023505A 1994-09-16 1994-09-16 Clock-doubling apparatus KR970000254B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940023505A KR970000254B1 (en) 1994-09-16 1994-09-16 Clock-doubling apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940023505A KR970000254B1 (en) 1994-09-16 1994-09-16 Clock-doubling apparatus

Publications (2)

Publication Number Publication Date
KR960011611A true KR960011611A (en) 1996-04-20
KR970000254B1 KR970000254B1 (en) 1997-01-08

Family

ID=19392968

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940023505A KR970000254B1 (en) 1994-09-16 1994-09-16 Clock-doubling apparatus

Country Status (1)

Country Link
KR (1) KR970000254B1 (en)

Also Published As

Publication number Publication date
KR970000254B1 (en) 1997-01-08

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