KR960010496B1 - Hdtv receiver - Google Patents

Abstract

a decoder (1) for restoring a compressed bit stream and outputting interlaced scanning type R, G and B video signals; a sequential scanning type converter (2) for converting the output signals of the decoder (1) into the sequential scanning type signals; a decimator (3) for converting the output signals of the sequential scanning type converter (2) into a format of 787.5 lines; a frame rate converter (4) for converting the frame rate of the output signals of the sequential scanning type converter (2) and the decimator (3); and the first multiplexer (5) for selectively outputting the output signals of the frame rate converter (4) in the desired format.

Description

HTV receiver

1 is a block diagram of an HDTV receiver according to the present invention.

2 is a detailed block diagram of the decoder of FIG.

3 is a detailed configuration diagram of the sequential scanning converter of FIG.

4 is a signal waveform diagram of a sequential scanning converter of FIG.

5 is a signal waveform diagram of a sequential scanning converter of FIG.

6 is a detailed block diagram of a 4: 3 vertical decimation part of FIG.

7 is a signal waveform diagram of each part of FIG.

8 is a detailed block diagram of a 4: 3 horizontal decimation unit of FIG.

9 is a signal waveform diagram of each part of FIG. 8;

10 is a detailed block diagram of the frame rate converter of FIG.

FIG. 11 is a signal waveform diagram of each part of FIG. 10; FIG.

* Explanation of symbols for main parts of the drawings

1: Decoder 2: Sequential Scanning Inverter

3: decimation device 4: frame rate converter

5,25,34,42,53,61,68: Multiplexer 6,7: Sequential Scan Converter

8,9: 4: 3 decimation section 10,11: frame rate conversion section

12 VLD and demultiplexer 13 inverse quantization unit

14 IDCT part 15: adder

16: slice buffer 17,66,67: frame memory

18: motion compensation unit 19: color difference signal interpolation unit

20: R, G, B converter 21, 22, 27: line delay

23,31,32,35,39,40,50,51,54,58,59: Adder

24,28,38,47,57: 1/2 divider

26: delay signal weight calculation unit 29, 37, 48, 56: 1/4 divider

30,36,49,55: 1/16 divider 33,41,52,60: Subtractor

43: memory 44: memory control unit

46: Latch 62: 1: 4 Demultiplexer

63: 3: 1 multiplexer 64: delayed pixel weight calculation unit

65: non-delay pixel weight calculation unit

The present invention relates to a receiver of a high definition television (HDTV), in particular an HDTV receiver capable of receiving a compressed bitstream of an interlaced video format and outputting not only an interlaced video format but also a progressively scanned video format. It is about.

In the US, the HDTV standard is designed to encode and decode a variety of images without restricting the video format to a single frame. In 1050-line interlaced scanning, the frame rate is 60 Hz and 1050 lines, and the frame rate is 24 Hz, 60 Hz, and 787.5 lines. It is known that a total of six formats are available with a scan rate of 24 Hz, 30 Hz, and 60 Hz.

At this time, the frame rate is 24Hz, 30Hz considering the film mode (Film Mode), because the transmission of the frame rate to 24Hz and 30Hz sequential scanning in the case of transmitting the movie film is efficient in many ways.

The image standard that can be transmitted in this manner also varies, and accordingly, the image standard that can be displayed may vary.

Accordingly, there is a need for a device capable of displaying one image standard that can be transmitted in various formats.

SUMMARY OF THE INVENTION An object of the present invention is to provide an HDTV receiver for outputting an interlaced scan format as well as an interlaced scan format in the HDTV.

In order to achieve the above object, the present invention provides a decoding means for reconstructing a compressed bitstream to output an R, G, B image of an interlaced scan, and a sequential scanning transform for converting a signal output from the decoding means into a sequential scan. Means for converting a signal output from the sequential scanning conversion means into a format of 787.5 lines, frame rate converting means for converting a frame rate of the signal output from the sequential scanning conversion means and the decimation means, and the And a first multiplexing means for selecting and outputting the signal output from the frame rate converting means according to a format required by the user.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of an HDTV receiver according to the present invention.

The HDTV according to the present invention is composed of a decoder 1, a sequential scanning converter 2, a decimation device 3, a frame rate converter 4 and a multiplexer 5 as shown in FIG. 1050-line interlaced video signal with frame rate of 60Hz, 1050-line interlaced video signal with frame rate of 60Hz, 1050-line progressive video frame rate with 60Hz frame rate and 787.5-line sequential scan frame Converts to 60Hz video signal and outputs it.

The decoder 1 reconstructs the compressed bitstream and outputs interlaced R, G, and B video signals.

The sequential scanning converter 2 is composed of two sequential scanning converters 6 and 7 for inputting a signal output from the decoder 1 to divide each frame into two fields so that each field is divided. Converts to progressive scan frames.

The decimation apparatus 3 is composed of two 4: 3 decimation sections 8 and 9 to convert a signal output from the sequential scanning converter 2 into a format of 787.5 lines.

The frame rate converter 4 is a frame rate converter 10 for converting a frame rate of a signal output from the sequential scanning converter 2 and a frame rate of a signal output from the decimation device 3. It consists of a frame rate converter 11 for converting the.

The multiplexer 5 selects and outputs an image format selected according to a user's request from among signals output from the frame rate converters 10 and 11 of the decoder 1 and the frame rate converter 4.

2 is a detailed block diagram of the decoder 1 of FIG.

As shown in FIG. 2, the decoder 1 includes a variable length decoder (VLD) and a demultiplexer 12, an inverse quantizer 13, an inverse discrete costne transform (IDCT) unit 14, an adder 15, The slice buffer 16, the frame memory 17, the motion compensator 18, the chrominance signal interpolator 19, and the R, G, and B converters 20 are included.

The VLD and demultiplexer 12 receives the compressed bitstream and converts it into a meaningful signal such as coefficient, macroblock type, motion information, and the like.

The dequantization unit 13 dequantizes the signals output from the VLD and the demultiplexer 12, and the IDCT unit 14 performs IDCT processing of the signals output from the dequantization unit 13.

The motion compensator 18 compensates for the motion by using the motion information output from the VLD and the demultiplexer 12, and the adder 15 is output from the IDCT unit 14 and the motion compensator 18. The signal is added to output the scanned image signal in a predetermined block unit.

The signal output from the adder 15 is stored in the frame memory 17 to compensate for the motion of the next frame, and is simultaneously input to the slice buffer 16 to scan the image signal scanned in units of blocks. .

The color difference signal interpolation unit 19 interpolates the signals output from the slice buffer 16 to the color difference signals U and V and inputs them to the R, G, and B converters 20.

The R, G, B converter 20 converts the Y, U, V signals output from the color difference signal interpolator 19 into R, G, B signals and outputs the converted signals.

3 is a detailed configuration diagram of the sequential scanning converters 6 and 7 of FIG. 1, and FIG. 4 is a signal waveform diagram of the sequential scanning converter 6 of FIG. 1, and FIG. 5 is a sequential scanning of FIG. It is a detailed block diagram of the expression conversion unit 7.

The signals output from the decoder 1 are simultaneously input to two sequential scan converters 6 and 7, and in each of the sequential scan converters 6 and 7, the output of the decoder 1 is frame-by-frame. Assuming this is done, odd and even fields in the frame are converted into sequential scan frames.

In other words, the progressive scan converters 6 and 7 output progressive scan images having a frame rate of 30 Hz.

In this case, the sequential scan converters 6 and 7 receive the same signal as the output of the decoder 1, but since two adjacent lines belong to different fields, the sequential scan frames are interpolated and replaced by interpolating lines corresponding to different fields. Can be converted to

As shown in FIG. 3, the sequential scanning converters 6 and 7 perform the above-described operation of the line delay units 21 and 22, the line delay unit 22 and the decoder 1 connected in series. An adder 23 and a half divider 24 and a multiplexer 25 for multiplexing the outputs of the line delay 21 and the half divider 24, respectively, to calculate the average from the output, Implement by replacing the line corresponding to the other field with the average between two adjacent lines of the corresponding field.

Since both fields are included in the input frame, the average between two adjacent lines of the corresponding field can be obtained through the two line delays 21 and 22.

The output of the 1/2 divider 24, which is an average between two lines, and the lines belonging to the corresponding field are summed and output through the multiplexer 25.

Signal waveforms showing the detailed operation of one sequential scan conversion unit configured as described above are shown in FIG.

Since the other sequential scanning converters change the lines belonging to the corresponding fields, the selection signal selected by the multiplexer 25 should be reversed. The output of the multiplexer 25 at that time is as shown in FIG.

As described above, the signal converted into 1050-line progressive scan is output to the decimation apparatus 3 for conversion into a progressive scan image of another format.

FIG. 6 is a detailed configuration diagram of the 4: 3 vertical decimation section of FIG. 1, and FIG. 7 is a signal waveform diagram of each part of FIG.

The two 4: 3 decimation sections 8 and 9 constituting the decimation apparatus 3 are each composed of 4: 3 vertical decimation sections and 4: 3 horizontal decimation sections.

As shown in FIG. 6, the 4: 3 vertical decimation unit includes a line delay unit 27, a delay signal weight calculation unit 26, a non-delay signal weight calculation unit 45, multiplexers 34 and 42, and an adder. 35, the memory 43, and the memory controller 44 convert the 1050 lines to 787.5 lines.

In this case, the converting method is a method of substituting a variable average according to a relative position of a scanning line of two formats.

That is, to reduce 4 lines to 3 lines, the first output line of the line is replaced by the first line of the 4 line unit of 4 inputs, and the second output line is the weighted average of the second and third lines of the 4 line unit of the input according to the relative position. Where we replace 0.69 and 0.31, and the third output line replaces the weighted average of the third and fourth lines of the input four-line unit, here 0.31 and 0.69.

If the weight is 0.69, this is because the relative output line position is close to the corresponding input line. If the weight is 0.31, the relative output line position is far from the corresponding input line.

The reason why we chose only 0.69 and 0.31 weights is to realize the ease of implementation by using an adder instead of a multiplier.

In this case, dividing by 2 is simply because it can be implemented without the need for additional hardware. 1/2 + 1/4 = 0.75, 1/4 + 1/16 = 0.3125, 1/2 + 1 / 4-1 / 16 = 0.6785.

The delay signal weight calculation unit 26 is a 1/2 divider 28, a 1/4 divider 29, a 1/16 divider 30, an adder 31, 32, and a subtractor 33. And through the 1/2 divider 28, 1/4 divider 29 and 1/16 divider 30, respectively, to the signal output delayed from the line delay 42. , 1/4, 1/16, add the outputs of the 1/2 divider 28 and 1/4 divider 29 through the adder 31, the 1/4 divider 29 And the output of the 1/16 divider 30 through the adder 32, and subtracts the difference between the output of the adder 31 and the output of the 1/16 divider 30. Obtain through.

That is, when the output of the 1/4 divider 29 and the 1/16 divider 30 is added through the adder 32, the weight is multiplied by 0.31, and the 1/2 divider 28 and the 1/4 divider The output of (29) is added through the adder 31 and the output of the 1/16 divider 30 is subtracted through the subtractor 33, thereby multiplying the weight by 0.69, thereby multiplying the weight by 0.31 and 0.69. Can be represented.

The multiplexer 34 selects a value obtained by multiplying the line delay 27, the weight of 0.31, which is the output of the adder 32, a value of 0.69, which is the output of the subtractor 33, and a value of 0, which is ground. Output the desired signal.

The non-delay signal weight calculation unit 45 includes a 1/2 divider 38, a 1/4 divider 37, a 1/16 divider 36, an adder 39, 40, and a subtractor 41. 1/1 through the 1/2 divider 38, 1/4 divider 37 and 1/16 divider 36, respectively, to the signal output from the sequential scanning converter 2; Multiplies 2, 1/4, 1/16, adds the outputs of the 1/2 divider 38 and the 1/4 divider 37 through the adder 39, and the 1/4 divider 37 ) And the output of the 1/16 divider 36 are added through the adder 40, and the difference between the output of the adder 39 and the output of the 1/16 divider 36 is obtained by the subtractor 41. Obtain through

That is, the sum of the outputs of the 1/4 divider 37 and the 1/16 divider 36 through the adder 40 is multiplied by a weight of 0.31, and the 1/2 divider 38 and 1 / 4, the output of the divider 37 is added through the adder 39, and the output of the 1/16 divider 36 is subtracted from the subtractor 41 is multiplied by a weight of 0.69.

The multiplexer 42 is a signal output from the sequential scanning converter 2, a value multiplied by a weight of 0.31, which is an output of the adder 40, a value multiplied by a weight of 0.69, which is an output of a subtractor 41, and a weight of ground 0. Select the value multiplied by and output the desired signal.

In this case, the sum of the weights multiplied by the signals selected by the multiplexers 34 and 42 should always be '1'.

The signals output from the multiplexers 34 and 42 are added through the adder 35 to form a weighted average, and the weighted average output from the adder 35 is a required line under the control of the memory controller 44. Only three of four lines are selected and written to the memory 44, and then read and output at the output speed.

The signal waveform showing the detailed operation of the 4: 3 vertical decimation unit configured as described above is shown in FIG.

FIG. 8 is a detailed configuration diagram of the 4: 3 horizontal decimation unit according to the present invention, and FIG. 9 is a signal waveform diagram of each part of FIG.

As shown in FIG. 8, the 4: 3 horizontal decimation unit includes a latch 46, a delay pixel weight calculator 64, a non-delay pixel weight calculator 65, multiplexers 53 and 61, and an adder 54. ), A 1: 4 demultiplexer 62 and a 3: 1 multiplexer 63 decimate the number of pixels per line in a 4: 3 ratio.

The 4: 3 horizontal decimation section operates almost the same on the same principle as the 4: 3 vertical decimation section (FIG. 6).

In other words, since the pixel is processed instead of the line, the latch is used instead of the line delay.

The delay pixel weight calculation unit 64 is a 1/2 divider 47, a 1/4 divider 48, a 1/16 divider 49, an adder 50, 51, and a subtractor 52. And a half divider 47, a quarter divider 48, and a 1/16 divider 49 to output pixel signals delayed from the latch 46, respectively. Multiply 1/4 and 1/16, add the outputs of the 1/2 divider 47 and the 1/4 divider 48 through the adder 50, and the 1/4 divider 48 The output of the 1/16 divider 49 is added through the adder 51, and the difference between the output of the adder 50 and the 1/16 divider 49 is obtained through the subtractor 52.

That is, adding the outputs of the 1/4 divider 48 and the 1/16 divider 49 through the adder 51 multiplies the weight 0.31, and divides the 1/2 divider 47 and the 1/4 divider. When the output of the unit 48 is added through the adder 50 and the output of the 1/16 divider 49 is subtracted through the subtractor 52, the weight is multiplied by 0.69, thereby multiplying the weight by 0.31 and 0.69. Can be effective.

The multiplexer 53 selects a value obtained by multiplying the weight of the latch 46 and the adder 51 by 0.31, the value of the subtractor 52 by the weight 0.69, and the ground 0 by the desired value. Output the signal.

The non-delayed pixel weight calculator 65 includes a 1/2 divider 57, a 1/4 divider 56, a 1/16 divider 55, an adder 58, 59, and a subtractor 60. And the 1/2 divider 57, 1/4 divider 56 and 1/16 divider 55 to the signal output from the 4: 3 vertical decimation unit (FIG. 6). Multiply by 1/2, 1/4, and 1/16, respectively, add the outputs of the 1/2 divider 57 and 1/4 divider 56 through the adder 58, and divide 1/4. Adds the output of the unit 56 and the 1/16 divider 55 through the adder 59, and subtracts the output difference of the 1/16 divider 55 from the output of the adder 58. To obtain.

That is, the sum of the outputs of the 1/4 divider 56 and the 1/16 divider 55 through the adder 59 is a value multiplied by 0.31, and the 1/2 divider 57 and 1 / 4, the output of the divider 56 is added through the adder 58, and the output of the 1/16 divider 55 is subtracted through the subtractor 60 is multiplied by a weight of 0.69.

The multiplexer 61 is a value obtained by multiplying the signal output from the 4: 3 vertical decimator (Fig. 6), the weight of 0.31, which is the output of the adder 59, and the output of the subtractor 60, the weight of 0.69. And a value obtained by multiplying a weight of 0, which is ground, to output a desired signal.

In this case, the sum of the weights multiplied by the signals selected by the multiplexers 53 and 61 should always be '1'.

The signals output from the multiplexers 53 and 61 are added through the adder 54 to form a weighted average, and the weighted averages output from the adder 54 pass through the 1: 4 demultiplexer 62 to form a 4 phase. After dividing by), only the desired three phases are selected by the 3: 1 multiplexer 63 to finally obtain the desired output.

The signal waveform showing the detailed operation of the 4: 3 horizontal decimation unit configured as described above is shown in FIG.

FIG. 10 is a detailed configuration diagram of the frame rate converters 10 and 11 of FIG. 1, and FIG. 11 is a signal waveform diagram of each part of FIG.

The frame rate converters 10 and 11 are composed of frame memories 66 and 57 and a multiplexer 68, as shown in FIG. 10, so that the outputs of the 4: 3 decimators 8 and 9, Alternatively, the outputs of the respective frame memories 66 and 67 are framed by the multiplexer 68 by reading the outputs of the sequential scanning converters 6 and 7 into the frame memories 66 and 67, respectively, and reading at twice the speed. Select and output alternately.

Signal waveforms showing the detailed operation of the frame rate converters 10 and 11 configured as described above are shown in FIG.

Accordingly, the signal output from the frame rate converter 10 is a video signal having a frame rate of 60 Hz in 1050 line sequential scanning, and the signal output from the frame rate converter 11 is a frame in a 787.5 line sequential scanning. A video signal having a rate of 60 Hz, a signal output from the decoder 1 is a video signal having a frame rate of 60 Hz in a 1050-line interlaced scan, and the multiplexer 5 is the decoder 1 and a frame rate converter. Video signals having a total of three formats output from (4) are selected and output from the multiplexer 5 according to the user's request.

The present invention configured and operated as described above has an effect of being able to display in various image formats separately from the monitor.

Claims (17)

Decoding means (1) for restoring the compressed bitstream and outputting interlaced scan R, G, and B images, and sequential scanning conversion means (2) for converting the signals output from the decoding means (1) into sequential scanning Decimation means (3) for converting the signal output from the sequential scanning conversion means (2) into a format of 787.5 lines, of the signal output from the sequential scanning conversion means (2) and the decimation means (3). Frame rate converting means (4) for converting the frame rate and first multiplexing means (5) for selecting and outputting according to a format required by a user from the signal output from said frame rate converting means (4). HDTV receiver. The apparatus of claim 1, wherein the decoding means (1) is output from a variable length decoder (VLD) and demultiplexing means (12) and the VLD and demultiplexing means (12) for converting an input bitstream into a meaningful signal. From inverse quantization means 13 for inversely quantizing the signal, IDCT processing means 14 for inverse discrete cosine transform (IDCT) processing the signal output from the inverse quantization means 13, and the VLD and demultiplexing means 12. A motion compensating means 18 for compensating for motion by comparing the output signal with the frame data before one frame, an adding means 15 for adding the outputs of the motion compensating means 18 and the IDCT means 15, and the adding means. Frame memory means 17 for storing a signal output from (15) and providing this stored signal to the motion compensating means 18 as frame data one frame earlier, and outputting from said adding means 15; A slice buffer means 16 for converting a signal in units of lines, a color difference signal interpolation means 19 for chrominance interpolating a signal output from the slice buffer means 16, and a signal output from the color difference signal interpolation means 19 The HDTV receiver, characterized in that consisting of the R, G, B conversion means for converting the R, G, B signal. The method according to claim 1, wherein the sequential scanning converting means (2) is a first and second sequential scanning converting portions (6, 7) for dividing a frame into two fields and converting each field into a sequential scanning expression, respectively. HDTV receiver, characterized in that configured. The decimation means (3) according to claim 1, wherein the decimation means (3) converts the signals output from the sequential scanning conversion means (2) into a format of 787.5 lines, respectively. 9) HDTV receiver, characterized in that consisting of. 2. The frame rate converting means (4) according to claim 1, wherein said frame rate converting means (4) comprises a first frame rate converting portion (10) and said decimation means (3) for converting a frame rate of a signal output from said sequential scanning converting means (2). And a second frame rate converter (11) for converting a frame rate of a signal output from the signal. 4. The first and second sequential scanning converters (6, 7) according to claim 3, characterized in that the first line delay means (21) for delaying the signal output from the decoding means (1), the first line delay Second line delay means (22) for delaying the signal output from the means (21), addition means (23) for calculating an average of the signals output from the decoding means (1) and the second line delay means (22); HDTV receiver, characterized in that it comprises a second division means (24), a second multiplexing means (25) for multiplexing the signal output from the first delay means (21) and the half division means (24). . 5. The four-third horizontal decimation of claim 4, wherein the first and second four-third decimations (8,9) are connected to 4: 3 vertical decimation means and 4: 3 vertical decimation means, respectively. HDTV receiver, characterized in that consisting of means. 6. The apparatus of claim 5, wherein the first and second frame rate converters (10, 11) comprise first and second frame memory means (66,67) and the first and second frame memories for storing input signals. And a second multiplexing means (68) for alternately selecting and outputting the output of the means (66,67) in units of frames. 7. The second and second multiplexing means (25) according to claim 6, wherein the second multiplexing means (25) transmits the signals output from the first delay means (21) and the half division means (24) to the first and second sequential scanning converters (6). , 7) HDTV receiver, characterized in that the multiplexing in the reverse order. 8. The signal output according to claim 7, wherein the 4: 3 vertical decimation means comprises a line delay means 27 for delaying the signal output from the sequential scanning conversion means 2, and a signal output from the line delay means 27. Delay signal weight calculation means 26 for outputting a value multiplied by each weight, and non-delay signal weight calculation means 45 for outputting a value obtained by multiplying each weight by a signal output from the sequential scanning conversion means 2. A second multiplexing means (34) which selects among the delay signal weight calculating means (26), the line delay means (27), and a signal output from ground, the non-delay signal weight calculating means (45), and the sequential scanning conversion means. A first multiplexing means (35) which adds an output signal of the second and third multiplexing means (33) and the third and multiplexing means (42) to select from (2) and a signal output from ground; Output from 35 Memory means (43) and the HDTV receiving device being configured as a memory control means (44) for controlling the memory means 43 for storing signals. 8. The method according to claim 7, wherein the 4: 3 horizontal decimation means comprises: latch means 46 for delaying a signal output from the 4: 3 vertical decimation means, and a weight for each of the signals output from the latch means 46; A delay pixel weight calculation means 64 for outputting a value obtained by multiplying the non-delay pixel weight calculation means 65 for outputting a value obtained by multiplying respective weights by a signal output from the 4: 3 vertical decimation means, and the delay pixel From the weight calculation means 64 and the latch means 46 and the second multiplexing means 53 for selecting a signal output from the ground, from the non-delayed pixel weight calculation means 65 and 4: 3 vertical decimation means and ground. From the third multiplexing means 61 for selecting an output signal, the first adding means 54 and the first adding means 54 for adding signals output from the second and third multiplexing means 53 and 61. God output 1: 4 demultiplexing means 62 for demultiplexing 1: 4 and 3: 1 multiplexing means 63 for multiplexing the signal output from the 1: 4 demultiplexing means 62 to 3: 1. HDTV receiver, characterized in that. 11. The apparatus of claim 10, wherein the delay signal weight calculating means (25) comprises: 1/2 division means (28) and line delay means (27) for dividing the signal output from the line delay means (27) by half. 1/4 division means 29 for dividing the output signal by 1/4, 1/16 division means 30 for dividing the signal output from the line delay means 27 by 1/16, and the 1/2 division means Second addition means 31 for adding the outputs of the 28 and 1/4 division means 29, and third addition means for adding the outputs of the 1/4 division means 29 and 1/16 division means 30. (32), subtraction means (33) for calculating a difference between the outputs of the second adding means (31) and the 1/16 division means (30). 11. The non-delay signal weight calculating means (45) according to claim 10, wherein the non-delayed signal weight calculating means (45) divides the signal input from the sequential scanning conversion means (2) by half dividing means (38), and the sequential scanning conversion means. 1/4 division means 37 for dividing the signal input from (2) by 1/4, 1/16 division means 36 for dividing the signal input from the sequential scanning conversion means 2 by 1/16, Second addition means 39 for adding the outputs of the 1/2 division means 38 and the 1/4 division means 37, and the outputs of the 1/4 division means 37 and 1/16 division means 36 And a subtracting means (41) for calculating a difference between the outputs of the third adding means (40) and the output of the second adding means (39) and the 1/16 division means (36). 11. The method of claim 10, wherein the second and third multiplexing means (34, 42) is the sum of the weights multiplied by the signal output from the delay signal weight calculation means 26 and the non-delay weight value calculation means 45 is' HDTV receiver, characterized in that selected to be 1 '. 12. The apparatus of claim 11, wherein the delay pixel weight calculation means (65) is output from the half division means (47) and the latch means (46) for dividing the signal output from the latch means (46) by one half. 1/4 division means 48 for dividing the signal by 1/4, 1/16 division means 49 for dividing the signal output from the latch means 46 by 1/16, and the 1/2 division means 47 And second adding means 50 for adding the output of the 1/4 division means 48, and third adding means 51 for adding the outputs of the 1/4 division means 48 and the 1/16 division means 49. And subtraction means (52) for calculating a difference between the outputs of the second adding means (50) and the 1/16 division means (49). 12. The non-delay pixel weight calculating means (65) according to claim 11, wherein the non-delay pixel weight calculating means (65) divides the signal output from the 4: 3 vertical decimation means into half dividing means (57), and the 4: 3 vertical decimation. 1/4 division means 56 for dividing the signal output from the simulation means by 1/4, 1/16 division means 55 for dividing the signal output from the 4: 3 vertical decimation means by 1/16, and 1 Second addition means 58 for adding the outputs of the / 2 division means 57 and the 1/4 division means 56, and adding the outputs of the 1/4 division means 56 and the 1/16 division means 57; And a subtraction means (60) for calculating a difference between the third adding means (59) and the output of the second adding means (58) and the 1/16 division means (55). 12. The method of claim 11, wherein the second and third multiplexing means (53, 61) is the sum of the weights multiplied by the signal output from the delay pixel weight calculation means 64 and the non-delay pixel weight calculation means (65) HDTV receiver, characterized in that selected to be '1'.