KR960007202B1 - Hdtv receiver - Google Patents

Abstract

a decoding means 2 for regenerating and selecting on coefficients corresponding to the lower band from inputted compressed bit streams; a sequential scan type converting means 3 for converting the output signal of the decoding means 2 into a sequential scan type video signal when the output signal is an interlace scan type video signal; a frame rate converting means for converting the frame rate of the output signal from the decoding means 2 into a predetermined frame rate; a first multiplexing means 6 for selectively outputting one of the output signals from the decoding means 2, the sequential scan type converting means 3, and the frame rate converting means; an interpolating means 7 for interpolating the output signal from the first multiplexing means 6; a second multiplexing means 8 for selectively outputting one of the output signals from the first multiplexing means 6 and the interpolating means 7; a display processing means 9 for processing to display the output signal from the second multiplexing means 8; and a multiplexer control means 10 for controlling the first and second multiplexing means 6 and 8.

Description

HTV receiver (HDTV) receiver

1 is a block diagram of an HDTV receiver according to the present invention.

2 is a detailed configuration diagram of the decoder of FIG.

3 a, b, and c are operational states of the memory of FIG.

4 is an operational state diagram of the multiplexer controller of FIG.

5 is a detailed configuration diagram of the sequential scanning converter of FIG.

6 is a signal waveform diagram of each part of FIG.

7 is a detailed block diagram of the 1: 2 frame rate converter of FIG.

8 is a signal waveform diagram of each part of FIG.

9 is a detailed configuration diagram of the 2: 5 frame rate converter of FIG.

10 is a signal waveform diagram of each part of FIG.

11 is a detailed block diagram of the 3: 4 vertical interpolator of FIG. 1.

12 is a signal waveform diagram of each part of FIG.

13 is a detailed block diagram of the 3: 4 horizontal interpolator of FIG. 1.

14 is a signal waveform diagram of each part of FIG.

FIG. 15 is a detailed configuration diagram of the display processor of FIG.

* Explanation of symbols for main parts of the drawings

1: signal input 2: decoder

3: sequential scanning converter 4: 1: 2 frame rate converter

5: 2: 5 frame rate converter

6, 8, 27, 28, 30, 32, 39, 45, 49, 53, 60, 66: multiplexer

7: 3: 4 interpolation unit 9: display processing unit

10: multiplexer control unit 11: VLD and demultiplexer

12: macroblock memory 13: inverse quantization unit

14: IDCT section 15, 17, 37, 38: memory

16, 25, 41, 52, 54, 61, 63, 65: adder

18, 29, 34, 36: frame memory

19: motion compensator 20, 26, 44, 50, 58, 62: 1/2 division

23, 24, 42: line delay unit 33: moving unit and stop unit discrimination unit

40: Memory control section 43, 51, 57, 64: 1/4 division

46, 47: FIFO 48: FIFO control unit

56, 59: Latch 67: 1: Demultiplexer

68: 4: 1 multiplexer 70: color difference signal interpolator

71: R, G, B conversion unit 72: synchronization signal processing unit

73: DAC 74: delay signal weight calculation unit

75: non-delay signal weight calculation unit 76: delay pixel weight calculation unit

77: non-delay pixel weight calculation unit

The present invention relates to a receiver of a digital high definition television (HDTV), and more particularly to a simplified HDTV receiver for use when the monitor size is not large.

In the United States, the HDTV standard is designed to encode and decode various video formats without limiting the video format to one. In 1050-line interlaced scanning, the frame rate is 60 Hz and 1050 sequential scanning, and the frame rate is 24 Hz, 30 Hz, and 787.5 lines. It is known that the frame rate is available in six formats of 24Hz, 30Hz and 60Hz.

At this time, the frame rate is 24Hz, 30Hz considering the film mode (Film Mode), because the transmission of the frame rate to 24Hz and 30Hz sequential scanning in the case of transmitting the movie film is efficient in many ways.

The images that can be transmitted in this way will vary, while in general, the image specifications displayed on the monitor will be limited to one that suits the characteristics of the monitor.

Therefore, even if any of the above six image formats is input, a device for decoding the image and converting it to a display format and displaying it on a monitor is essential for an HDTV receiver.

The high-definition effect of the HDTV may appear on a large screen, that is, 50 inches or more, and the monitor of a smaller size may not show a big difference even when displaying a video image that is slightly lower than the resolution of the actual transmitted image.

However, when the HDTV receiver using a small size monitor is applied in full-spec, there is a problem that it is difficult to feel the effect of the difference in resolution while increasing the economic burden of the user.

In order to solve the above problems, the present invention reduces the processing speed and resolution of the decoder, and the monitor is 525-line sequential scanning so that the resolution is about halfway between the HDTV and the conventional TV. The purpose of the present invention is to provide an HDTV receiver that brings in effect.

In order to achieve the above object, the present invention provides decoding means for selecting and restoring only coefficients corresponding to a low range from an input compressed bitstream, and a sequential scanning video signal when the signal output from the decoding means is an interlaced video signal. A sequential scan conversion means for converting the frame rate conversion means, the frame rate conversion means for converting the frame rate of the signal output from the fraud decoding means into a constant frame rate, the decoding means, the sequential scan conversion means and the frame rate outputted from the change means First multiplexing means for selecting and outputting from among signals, second multiplexing means for selecting and outputting from signals output from the first multiplexing means, and display processing means for processing to display a signal output from the second multiplexing means And the first and second multiplexing numbers. And it characterized in that the configuration including the multiplexer control means for controlling the.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an HDTV receiver according to the present invention.

As shown in FIG. 1, the HDTV receiver according to the present invention includes a decoder 2, a sequential scan converter 3, a frame rate converter 4, 5, a multiplexer 6, 8, 3: 4 It consists of an interpolation unit 7, a display processing unit 9, and a multiplexer control unit 10.

The decoder 2 selects and restores only the 4 × 4 coefficients corresponding to the low frequencies from the coefficients of the 8 × 8 block unit and discards the remaining ones to reduce the processing speed to 1/4, and the output of the recorder 2 is input. In the case of the interlaced scan of 1050 lines, the interlaced scan image of 252 lines becomes a sequential scan image of an input of 787.5 lines, and a progressive scan image of 36 lines of an active region.

When the output of the recorder 2 is an interlaced scan, it is converted into a progressive scan image by the progressive scan converter 3, and when the frame rate is not 60 Hz, the 1: 2 or 2: 5 frame rate converter The frame rate is converted at (4, 5), and the multiplexer 6 selects from the outputs of the decoder 2, the sequential scanning converter 3 and the frame rate converter 4, 5 according to the input image. In this case, when the selected image is not in the format of 525 lines, the interpolation unit 7 passes through the 3: 4 interpolation unit 7 to interpolate in the 525 line format.

The 3: 4 interpolation unit 7 is composed of a 3: 4 vertical interpolation unit and a 3: 4 horizontal interpolation unit.

The multiplexer 8 selects an output of the multiplexer 6 and the 3: 4 interpolator 7 according to an input image and outputs the output to the display processor 9.

The display processing unit 9 generates R, G, B (red, green, blue) signals and synchronization signals suitable for the final display from the signals output from the multiplexer 18 and outputs them to the monitor.

FIG. 2 is a detailed configuration diagram of the decoder 2 of FIG. 1, and FIG. 3 abc is an operational state diagram of the memories 12, 15 and 17 of FIG.

The decoder 2 includes a variable length decoder (VLD) and a demultiplexer 11, a macroblock memory 12, an inverse quantizer 13, and an inverse discrete cosine transform (IDCT) unit (shown in FIG. 14), memory (15, 17), adder (16), frame memory (18), motion compensator (19), and half division (20).

The VLD and demultiplexer 11 receives the compressed bit stream and converts it into a meaningful signal such as coefficients, macroblock types, motion information, and the like.

The macroblock memory 12 stores coefficients in units of macroblocks, as shown in FIG. 3A, and then reads and outputs only coefficients of 4x4 blocks corresponding to low frequencies from each macroblock b.

The de-quantizer 13 dequantizes the macroblock type and the quantization level output from the VLD and the demultiplexer 11 and the coefficients output from the macroblock memory 12 into 4 × 4 block units as input. In this case, the dequantization rate is also reduced to 1/4 of the sampling frequency of the input image.

The output of the inverse quantization unit 13 is applied to the IDCT unit 14 to perform IDCT processing, and the processing unit of the IDCT is 4 × 4 block units.

The scan of the output of the IDCT unit 14 in units of 4x4 blocks through the memory 15 is adapted to scanning in units of scanning blocks, i.e. 8x8 blocks, of signals output through motion compensation.

That is, as shown in Fig. 3b, scanning is performed in units of 4x4 blocks at the time of input, and at units of 8x8 blocks at the time of output.

The motion information output from the VLD and the demultiplexer 11 is 1/2 scaled through the 1/2 divider 20 and then motion compensated by the motion compensator 19 and stored in the frame memory 18. .

The adder 16 adds the outputs of the frame memory 18 and the memory 15 to restore an image, and the restored signal is input to the frame memory 18 and the memory 17.

The frame stored in the frame memory 18 corresponds to one-fourth the size of the frame of the HDTV, and the memory 17 outputs an image output in 8 × 8 block units as shown in FIG. 3C. Write in block units (e) and convert in line units (f).

4 is an operational state diagram of the multiplexer control unit 10 of FIG.

As shown in FIG. 4, the multiplexer controller 10 receives a video signal input together with the decoder 2 and controls a multiplexer 6, 8 according to the video signal S ₀ S ₁ . The multiplexers 6 and 8 select and output an input signal according to the control signals S ₀ and S ₁ .

That is, when the input image signal is 1050 lines interlaced scanning and the frame rate is 60 Hz, the control signal S ₀ controlling the multiplexer 6 is controlled to select the output of the sequential scanning converter 3 as '00'. The control signal S ₁ for controlling the multiplexer 8 is controlled to select the output of the multiplexer 6 as '1'.

In addition, when the input image signal is a 1050-line sequential scan type and the frame rate is 30 Hz, the control signal S ₀ is set to '01' so as to select the output of the 1: 2 frame rate converter 4 and the control signal ( S ₁ ) controls to select the output of the multiplexer 6 as '1'.

In addition, when the input image signal is a 1050-line sequential scan type and the frame rate is 24 Hz, the control signal S ₀ is set to '10' so as to select the output of the 2: 5 frame rate converter 5 and the control signal ( S ₁ ) controls to select the output of the multiplexer 6 as '1'.

Further, when the input image signal is a 787.5-line sequential scan type and the frame rate is 60 Hz, the control signal S ₀ is controlled to select the output of the decoder 2 at '11', and the control signal S ₁ is' Control to select the output of the 3: 4 interpolator 7 as 0 '.

In addition, when the input image signal is a 787.5-line sequential scanning formula and the frame rate is 30 Hz, the control signal S ₀ is set to '01' so as to select the output of the 1: 2 frame rate converter 4 and the control signal S ₁ ) controls to select the output of the 3: 4 interpolator 7 as '0'.

In addition, when the input image signal is a 787.5-line sequential scan type and the frame rate is 24 Hz, the control signal S ₀ is set to '10' to control the output of the 2: 5 frame rate changing unit 5 and the control signal S ₁ ) controls to select the output of the 3: 4 interpolator 7 as '0'.

FIG. 5 is a detailed configuration diagram of the sequential scanning converter 3 of FIG. 1, and FIG. 6 is a signal waveform diagram of each part of FIG.

As shown in FIG. 5, the sequential scan converter 3 includes line delay units 23 and 24, an adder 25, a 1/2 divider 26, and a multiplexer 27, 28, 30, 32. , Frame memories 29 and 31, and a moving part and a stop part discriminating part 33. As shown in FIG.

The sequential scanning equation changing unit 3 will be described on the assumption that the signal output from the decoder 2 is in a frame unit in which two fields are added together.

The signal 22 output from the decoder 2 is input to the line delay unit 23, the output of the line delay unit 23 is again input to the line delay unit 23, and the adder 25. The signal output from the adder and the signal output from the line delay unit 24 are added, and the 1/2 division 26 divides the output of the adder 25 by 1/2.

That is, the average between lines belonging to the same field is calculated and output to the multiplexer 27. The moving unit and the stop unit 33 determine the lines as the moving unit and the stop unit by using signals such as the macroblock type and the motion information output from the decoder 2. The multiplexer 27 is controlled to interpolate the scanned lines of the field and, in the case of a moving unit, to interpolate the line average of the corresponding field.

That is, the multiplexer 27 selects the output of the 1/2 division 26 in the case of the moving part according to the control signals output from the moving part and the stop part discriminating part 33, and in the case of the stop part, the line delay. The output of the unit 23 is selected.

The output of the multiplexer 27 and the output of the line delay unit 23 are input to the multiplexers 28 and 30, and the outputs of the multiplexers 28 and 30 are input to the frame memories 29 and 31, respectively. The outputs of the frame memories 29 and 31 are input to the multiplexer 32.

That is, the multiplexers 28 and 30 perform switching to convert each field in the frame, that is, odd and even fields, into a sequential scanning frame. Each multiplexer 28 and 30 first corresponds to each field. A line, that is, the output of the line delay unit 23 is selected, and the next interpolated line, that is, the output of the multiplexer 27 is selected.

As described above, an image converted from each field into a sequential scanning frame is stored in the frame memories 29 and 31, and then repeatedly read two times of a frame for one frame period at twice the speed, and is read by the multiplexer 32. By alternately selecting and outputting, a 60Hz progressive scan image is output.

The signal waveform showing the detailed operation of the sequential scan converter 3 configured as described above is as shown in FIG.

FIG. 7 is a detailed configuration diagram of the 1: 2 frame rate converter 4 of FIG. 1, and FIG. 8 is a signal waveform diagram of each part of FIG.

The 1: 2 frame rate converter 4 is composed of a frame memory 34 as shown in FIG. 7, and doubles the speed by using the frame memory 34 as shown in FIG. 8. Quickly read and convert 30Hz frame rate to 60Hz.

FIG. 9 is a detailed configuration diagram of the 2: 5 frame rate converter 5 of FIG. 1, and FIG. 10 is a signal waveform diagram of each part of FIG.

The 2: 5 frame rate converter 5 connects the memories 37 and 38 to the frame memory 36 which receives the output of the decoder 2 as shown in FIG. The multiplexer 39 is connected to an output terminal of the 37 and 38, and the memory control unit 40 is connected to the frame memory 36 and the memory 37 and 38 to convert a frame rate of 24 Hz to 60 Hz. .

The frame memory 36 converts the signal 35 input from the decoder 2 into a frame rate of 1: 2 according to the control unit of the memory control unit 40, and then, in the memory 37, 38, the memory control unit ( Under the control of 40), the signal is converted to the 4: 5 frame rate and output to the multiplexer 39.

That is, as shown in FIG. 10, the output of the frame memory 36 is divided into units of every four frames, only the first frame is written to the memory 37, and only one frame is read at an output speed after a predetermined delay. Four consecutive frames are written to (38) and read from the memory 38 as soon as reading is finished in the memory 37. If reading from the memory 37 is always performed, the memory 38 should only write and stop reading. .

That is, the memory controller 40 controls the read and write operations of the memories 37 and 38 and the frame memory 36 as described above.

FIG. 11 is a detailed configuration diagram of the 3: 4 vertical interpolator of FIG. 1, and FIG. 12 is a signal waveform diagram of each part of FIG.

As shown in FIG. 11, the 3: 4 vertical interpolator includes a line delay unit 42, a delay signal weight calculator 74, a non-delay signal weight calculator 75, a multiplexer 45, 49, 53, The adder 54, the FIFOs 46 and 47, and the FIFO control unit 48 convert the output of the decoder 2 to 525 lines when the transmitted image format is 787.5 lines and the active region is 720 lines.

The delay signal weight calculation unit 74 is composed of a quarter division 43, a 2/1 division 44, and an adder 41, and multiplies the signals output from the line delay unit 42 by weights, respectively. . The non-delay signal weight calculation unit 75 includes a quarter divider 51, a half divider 50, and an adder 52 to multiply the weights of the signals output from the multiplexer 6.

That is, the 3: 4 vertical interpolator is for interpolating at a ratio of vertical lines 3: 4, and interpolates with a weighted average between lines using an adder without using a multiplier.

In other words, instead of using a multiplier, only divide by two exponents and adders are used. For example, averaging means is calculated using 1/2 = 0.5, 1/4 = 0.25, and 1/2 + 1/4 = 0.75.

The line delay unit 42 delays the output of the multiplexer 6 and inputs it to the 1/2 divider 44 and the 1/4 divider 43 to the divide adder 41, respectively. Add the outputs of two divisions 44 and one quarter division 43.

The multiplexer 45 selects among the outputs of the 1/2 divider 44, the 1/4 divide 43, and the adder 41.

The signal which is not delayed and output from the multiplexer 6 is input to the 1/2 divider 50 and the 1/4 divider 51 and divided respectively, and added to the adder 52.

The multiplexer 53 selects among the outputs of the adder 52, the half divider 50 and the quarter divider 51.

The signals output from the multiplexers 45 and 53 are added to the adder 54 and input to the FIF 47, and the signals output from the line delay unit 42 are input to the FIFO 46 and then the multiplexer 49. ) Is selected and output.

The operation of the 3: 4 interpolation unit 7 configured as described above is as follows.

The signal delayed through the line delay unit 42 is multiplied by a weight through the quarter division 43, the half division 44, and the adder 41 in order to obtain a weighted average, and thus the multiplexer 45. The signal selected through the multiplier 53 is also multiplied by the weights through the 1/2 divider 50, 1/4 divider 51 and adder 52. In this case, the sum of the weights multiplied by the signals selected by the multiplexers 45 and 53 should be always '1'.

That is, the order of the multiplied weights of the signals selected by the multiplexer 45 is selected in the order of 0.25, 0.5, and 0.75, that is, the order of 1/4 division 43, 1/2 division 44, and adder 41. Are repeated, and the order of the multiplied weights of the signals selected by the multiplexer 53 is 0.75, 0.5, 0.25 in that order: adder 52, 1/2 divide 50, 1/4 divide 51 The selection will be repeated.

When the output of the multiplexers 45 and 53 is added to the adder 54, a weighted average is output, and the output of the line delay unit 42 and the weighted average output of the adder 54 are transmitted to the FIFOs 46 and 47. After each is stored, it is selected by the multiplexer 49 and output.

That is, the output of the line delay unit 42 is divided into units of every three lines, and then only the first line is stored in the FIFO 46, delayed for a predetermined time, and then read at an output speed and weighted by another FIFO 47 as soon as one line is read. The averaged lines are read and summed in the multiplexer 49.

The FIFO control unit 48 for controlling the FIFOs 46 and 47 outputs a read and write enable signal for controlling reading and writing of the FIFOs 46 and 47 as shown in FIG. Enables final output of vertically interpolated signals.

FIG. 13 is a configuration diagram of a 3: 4 horizontal interpolation unit of FIG. 1, and FIG. 14 is a signal waveform diagram of each part of FIG.

The 3: 4 interpolation part 7 of FIG. 1 is composed of a 3: 4 vertical interpolation part, a 3: 4 vertical interpolation part, and a 3: 4 horizontal interpolation part, as shown in FIG. 13. Latches 56 and 59, delayed pixel weight calculator 76, non-delayed pixel weight calculator 77, adder 61, multiplexers 60 and 66, 1: 3 multiplexer 67 and 4: 1 multiplexer. 68, and interpolates horizontally with a weighted average similarly to the 3: 4 vertical interpolation section.

The delay pixel weight calculator 76 includes a quarter divider 57, a half divider 56, and an adder 63 to multiply the signal output from the latch 56 by weights.

The non-delay pixel weight calculator 77 is composed of a quarter divider 64, a half divider 62, and an adder 65, and multiplies the weights of the signals output from the multiplexer 6.

The latch 56 is delayed by the pixel, and the signal delayed through the latch 56 is multiplied by the weights through the quarter division 57 and the half division 58 in a weighted average method. In addition, the adder 63 is selected through the multiplexer 60.

At the same time, the signal whose pixel is not delayed through the latch 56 is multiplied by the weight through the 1/2 division 62 and the quarter division 64 and added by the adder 65 through the multiplexer 66. Is selected.

In this case, the sum of the weights multiplied by the signals selected by the multiplexers 60 and 66 should always be '1'.

That is, the order of the multiplied weights of the signals selected by the multiplexer 60 is selected in the order of 0.25, 0.5, and 0.75, that is, in the order of 1/4 division 57, 1/2 division 58, and adder 63. The order of the multiplied weights selected by the multiplexer 66 is repeated in the order of 0.75, 0.5, 0.25, that is, in the order of the adder 63, the half division 58, and the quarter division 57. Choose.

The outputs of the multiplexers 60 and 66 are added by the adder 61 to a weighted average and output to the 1: 3 demultiplexer 67.

The 1: output of the demultiplexer 67 and the output of the latch 59 for delaying the pixel of the signal input from the multiplexer 6 are input to the 4: 1 multiplexer 68 and the final output is 3: 4 horizontal interpolated. can do.

The signal waveform diagram showing the detailed operation process of the 3: 4 horizontal interpolation unit configured as described above is shown in FIG. 6.

FIG. 15 is a detailed configuration diagram of the display processor 9 of FIG.

As shown in FIG. 15, the display processor 9 includes a color difference signal interpolator 70, an R, G, and B converter 71, a synchronization signal processor 72, and a digital analog converter (DAC) 73. It is composed of

The color difference signal interpolator 70 interpolates the color difference signals U and V to have the same bandwidth as the luminance signal, and the R, G, and B converters 71 are output from the color difference signal interpolator 70. The YUV signal is converted into R, G, and B signals, and the synchronization signal processor 72 generates a synchronization signal required by the monitor by using the signal output from the R, G, and B converters 71. The DAC 73 converts the signal output from the synchronization signal processing unit 72 into an analog signal and outputs the analog signal to the monitor.

The present invention configured and operated as described above has an economical effect in terms of price without any difference in resolution by displaying 525-line progressive scan images on a monitor having a size of about 30 inches in an HDTV that transmits images of various formats. Can bring

Claims (32)

Decoding means (2) for selecting and restoring only coefficients corresponding to the low range from the compressed bitstream input, and converting the signals output from the decoding means (2) into sequential scanning video signals when the signals are interlaced video signals. Sequential scanning conversion means (3), frame rate conversion means for converting the frame rate of the signal output from said decoding means (2) into a constant frame rate, said decoding means (2), sequential scanning conversion means (3) and First multiplexing means (6) for selecting and outputting among the signals output from the frame rate converting means (6), interpolation means (7) for interpolating the signal output from the first multiplexing means (6), and the first multiplexing means (6) And the second multiplexing means (8) for selecting and outputting among the signals output from the interpolation means (7), for displaying the signal output from the second multiplexing means (8). And a multiplexer control means (10) for controlling the display processing means (9) for processing and said first and second multiplexing means (6,8). A frame rate changing means (4) for converting a signal having a frame rate of 30 Hz to 60 Hz, and a frame rate for converting a signal having a frame rate of 24 Hz to 60 Hz. HDTV receiver, characterized in that the conversion means (5). The HDTV receiver as claimed in claim 1, wherein said interpolation means (7) comprises 3: 4 vertical interpolation means and 3: 4 horizontal interpolation means. The apparatus of claim 1, wherein the decoding means (2) is output from a variable length decoder (VLD) and demultiplexing means (11) and the VLD and demultiplexing means (11) for converting a compressed bit stream into a meaningful signal. Inverse quantization means (13) for inverse quantization using a signal output from the macroblock memory means (12), the signal output from the macroblock memory means (12), and the VLD and demultiplexing means (11). ), Motion compensation for compensating using motion information output from the IDCT means 14 and the VLD and the demultiplexing means 11 for IDCT (Inverse Discrete Cosine Transform) processing of the signal output from the inverse quantization means 13. Means 19, frame memory means 18 for storing signals output from said motion compensating means 19, and signals output from said IDCT means 14 for said frame memory. A first memory means 15 for converting the signal output from the means 18 in units of scanning blocks, and a signal output from the first memory means 15 and the frame memory means 18 to add the signal; And a second memory means (17) for converting the signal of the block unit output from the adding means (16) to the line unit. The method of claim 1, wherein the sequential scanning conversion means (3) comprises: first line delay means (23) for delaying the signal output from the decoding means (2) on a line basis, and the first line delay means (23). Second delay means (24) for delaying the signal output from the line unit, and adding means (25) for calculating the average between lines using the signals output from the decoding means (2) and the second line delay means (24). ) And 1/2 dividing means 26, a moving part and a stop part discriminating means 33 for discriminating a moving part and a stop part by using the signal output from the decoding means 2, and a moving part and a stop part discriminating means. The third multiplexing means 27 and the third multiplexing means 27 and the first line, which select among the outputs of the first line delay means 23 and the half division means 26 under the control of (33). Fourth and fifth multi output signals selected from the delay means 23 as inputs First and second frame memory means 29 and 31 and the first and second storage means for storing signals output from the flexing means 28 and 30, the fourth and fifth multiplexing means 28 and 30, respectively. And a sixth multiplexing means (32) for alternately selecting and outputting signals output from the frame memory means (29,31). 3. The multiplexer control means (10) according to claim 2, wherein the multiplexer control means (10) outputs the sequential scan conversion means (3) by the first multiplexing means (6) when the input video signal is 1050 lines interlaced, and the frame rate is 60 Hz. And control the second multiplexing means (8) to select an output of the first multiplexing means (8). 3. The multiplexer control means (10) according to claim 2, wherein the multiplexer control means (10) is adapted to convert the first and second frame rate conversion means (4) when the input video signal has a frame rate of 30 Hz in 1050-line sequential scanning. And outputting the second multiplexing means (8) to select an output of the first multiplexing means (6). 3. The multiplexing control means (10) according to claim 2, wherein the multiplexing control means (10) is adapted to convert the 2: 5 frame rate conversion means (5) when the input video signal has a frame rate of 24 Hz in 1050 line sequential scanning. And outputting the second multiplexing means (8) to select an output of the first multiplexing means (6). 3. The multiplexing control means (10) according to claim 2, wherein the multiplexing control means (10) selects the output of the decoding means (2) when the input video signal is a 787.5-line sequential scan type and the frame rate is 60 Hz. And control the second multiplexing means (8) to select the output of the interpolation means (7). 3. The multiplexing control means (10) according to claim 2, wherein the multiplexing control means (10) is the first and second frame rate converting means (4) when the input video signal has a frame rate of 30 Hz in a 787.5-line sequential scanning manner. And the second multiplexing means (8) control the interpolation means (7) to select an output. 3. The multiplexing control means (10) according to claim 2, wherein the multiplexing control means (10) is the second multiplexing means (5) when the input image signal is a 787.5-line sequential scan type and the frame rate is 24 Hz. And the second multiplexing means (8) to control the complementary stage (7) to select an output. 3. An HDTV receiver according to claim 2, wherein said 1: 2 frame rate converting means (4) comprises frame memory means (34). 3. The frame memory means (36) according to claim 2, wherein said 2: 5 frame rate converting means (4) comprises: frame memory means (36) for converting a signal output from said decoding means (2) by 1: 2 frame rate, and said frame memory means (36) First and second memory means 37 and 38 for converting a signal output from the frame to a 4: 5 frame rate, and third multiplexing means for multiplexing a signal output from the first and second memory means 37 and 38; (39) and memory control means (40) for controlling said frame memory means (36) and said first and second memory means (37,38). 4. The interpolation means according to claim 3, wherein the 3: 4 vertical interpolation means weights the signal output from the line delay means (42) and the signal output from the line delay means (42) for delaying the signal output from the first multiplexing means (6). The delay signal multiplication means 74 multiplies the output signal from the first multiplexing means 6 by the weight of the non-delay signal weight calculation means 75 and the delay signal weight calculation means 74. An output from the third multiplexing means 45 for selecting, the fourth multiplexing means 53 for selecting a signal output from the non-delayed signal weight calculation means 75, and the third and fourth multiplexing means 45 and 53; A first FIFO means 47 for adding a signal to be added, a first FIFO means 47 for storing a signal output from the first adding means 54, and a second FIFO for magnetically outputting a signal output from the line delay means 42; Means 46, said first and And a fifth multiplexing means (49) for multiplexing signals output from the 2FIFO means (47, 46) and FIFO control means (48) for controlling the first and second FIFO means (47, 46). HDTV receiver. The method of claim 3, wherein the 4: 4 horizontal reinforcing means includes: first latch means 56 for delaying an input pixel, and second latch means 59 for delaying a signal output from the first latch means 56. Delay pixel weight calculation means 76 for multiplying the signal output from the first latch means 56 by weight, non-delay pixel weight calculation means 77 for multiplying the input pixel signal with a weight, and calculation of the delay pixel weight Third multiplexing means 60 for selecting an output signal of the means 76, fourth multiplexing means 66 for selecting an output signal of the non-delay pixel weight calculation means 77, and third and fourth multiplexing means A first adding means 61 for adding a signal output from 60, 66, a 1: 3 demultiplexing means 67 for demultiplexing a signal output from the first adding means 61, and the second latch means The output signals of the 59 and 1: 3 demultiplexing means 67 are far from each other. HDTV receiver, characterized in that consisting of four to one multiplexing means (68) for multiplexing. 2. The display device according to claim 1, wherein the display processing means (9) is a color difference signal interpolation means (70) for interpolating the color difference signal to have the same bandwidth as the luminance signal, and the signal output from the color difference signal interpolation means (70). R, G, B converting means 71 for converting into G and B signals, synchronizing signal generating means 72 for generating synchronizing means using a signal output from the R, G, B converting means 71 and the And a digital analog converter (DAC) means (73) for converting a signal output from the synchronization signal generating means (72) into an analog signal. 5. The HDTV receiver according to claim 4, wherein said macro block memory means (12) outputs only coefficients of 4x4 blocks corresponding to a low range from signals output from said DLD and demultiplexing means (11). 5. The HDTV receiver as claimed in claim 4, wherein the inverse quantization means (13) performs inverse quantization in units of 4x4 blocks. 5. The HDTV receiver according to claim 4, wherein the IDCT means (14) processes IDCT in units of 4x4 blocks. 5. The HDTV receiver according to claim 4, wherein said first memory means (15) converts the signal output from said IDCT means (14) in 8x8 block units. 5. The apparatus of claim 4, further comprising a half dividing means (20) for scaling the motion information output from the VLD and the demultiplexing means (11) and outputting the half information to the motion compensating means (19). HDTV receiver, characterized in that. 6. HDTV receiver according to claim 5, characterized in that said first and second frame memory means (29,31) are read twice in one frame for a long period of input at twice the speed. 13. The HDTV receiver according to claim 12, wherein the frame memory means (34) reads at twice the speed and converts the frame rate of 30 Hz to 60 Hz. The memory control means 40 divides the signal output from the frame memory means 36 into units of every four frames, writes the first frame into the first memory means 37, and writes the fourth frame. HDTV receiver, characterized in that the control to read and write five frames alternately written to the second memory means (38). 15. The delay signal weight calculating means (74) according to claim 14, characterized in that the delay signal weight calculating means (74) is divided from the first division means (43) and the line delay means (42) by which the signal output from the line delay means (42) is multiplied by a weight of 0.25. Half dividing means 44 multiplying the output signal by a weight of 0.5 and second adding means 41 adding the outputs of the quarter dividing means 43 and the half dividing means 14. HDTV receiver, characterized in that. 15. The method of claim 14, wherein the non-delay signal weighting means (75) comprises: 1/4 division means (51) for multiplying the signal output from the first multiplexing means (6) by a weight of 0.25, and the first multiplexing means ( A third division means 50 for multiplying the signal output from 6) by a weight of 0.5, and a third addition for adding the signal output from the quarter division means 51 and the half division means 50; HDTV receiver, characterized in that consisting of means (52). 15. The method of claim 14, wherein the third and fourth multiplexing means (45, 53) is the sum of the weights multiplied by the output signal of the delay signal weight calculation means 74 and the non-delay signal weight calculation means 75 is' HDTV receiver, characterized in that selected to be 1 '. 16. The method of claim 15, wherein the delay pixel weight calculation means (76) is a quarter division means (57) for multiplying a signal output from the first latch means (56) by a weight of 0.25, and the first latch means (56). And the second dividing means 63, which adds the outputs of the half dividing means 57 and the half dividing means 58 by multiplying the weight of 0.5 of the signal output from HDTV receiver, characterized in that configured to. 16. The non-delay pixel weight calculation means (77) according to claim 15, wherein the non-delay pixel weight calculation means (77) divides the input pixel signal by a weight of 0.25, and the division means (64) multiplies the input pixel signal by a weight of 0.5. And a second dividing means (65) for adding the outputs of the two dividing means (62) and the quarter dividing means (64) and the half dividing means (62). The sum of the weights multiplied by the output signals of the delayed pixel weight calculation means 76 and the non-delayed pixel weight calculation means 77 is equal to '3'. HDTV receiver, characterized in that selected to be 1 '. The third multiplexing means (45) according to claim 27, wherein the third multiplexing means (45) selects the output signal of the delay signal weighting means (74) in the order of multiplied weights of 0.25, 0.5, and 0.75. Selects the output signals of the non-delayed signal weight calculation means (75) in the order of multiplying the weights by 0.75, 0.5, and 0.25. 31. The method of claim 30 wherein the third multiplexing means (60) has a multiplied weight of 0.25, 0.5. The non-delay pixel weight calculating means 77 selects the output signal of the delay pixel weight calculating means 76 in the order of 0.75, and the fourth multiplexing means 66 multiplies the multiplied weights by 0.75, 0.5, and 0.25. HDTV receiver, characterized in that for selecting the output of.