KR960002047B1 - Image signal format converting method for h.d.t.v. - Google Patents

Abstract

The HDTV receiving device having 525 line sequential scanning monitor display image format comprises a decoder for decoding a compressed bit stream into an image signal; a sequential scanning converter for converting the image signal into a sequential scanning format; a first frame rate converter for converting the frame rate of the image signal into 30Hz; a first switching unit for selecting one of the image signals of the decoder and first frame rate converter and outputting an image signal of 30Hz by a 1050 line sequential scanning format; a second switching unit for selecting one of the image signals of the decoder and first frame rate converter and outputting an image signal of 30Hz by a 787.5 line sequential scanning format; a first and second vertical decimation units for converting the number of line per frame of the image signals of the first and second switching units; a first and second horizontal decimation units for converting the number of pixel per line of the signals of the first and second vertical decimation units; a third switching unit for selecting one of the image signals of the first and second horizontal decimation units and outputting an image signal of 30Hz by a 525 line sequential scanning format; a second frame rate converter for converting the frame rate of the image signal from the third switching unit into 60Hz; a display processing unit for converting the image signal output from the second frame rate converter; and a switching selection controller for controlling the first, second and third switching units.

Description

HDTV receiver with 525-line progressive scan monitor display and format conversion method

1 is a block diagram of an HDTV receiver according to the present invention.

2 is a view illustrating selection criteria of the switching unit of FIG.

FIG. 3a is a detailed block diagram of the switching selector of FIG.

FIG. 3B is a view showing the selection operation control reference of FIG. 3A;

4A is a detailed configuration diagram of the decoding unit of FIG.

4b is a structural diagram of a decoding unit.

5 is a diagram illustrating an example of a sequential scan conversion unit in FIG.

6 is a signal waveform diagram of each part of FIG.

7 is another embodiment of the sequential scan conversion unit of FIG.

8 is a signal waveform diagram of each part of FIG.

9 is a detailed configuration diagram of the frame rate change part of FIG.

10 is a signal waveform diagram of each part of FIG.

11 is a detailed configuration diagram of the vertical decimation part of FIG.

12 is a signal waveform diagram of each part of FIG.

13 is a detailed configuration diagram of the horizontal decimation unit of FIG.

14 is a signal waveform diagram of each part of FIG.

FIG. 15 illustrates an embodiment of the vertical decimation unit of FIG.

FIG. 16 is a signal waveform diagram of each part of FIG.

17 is another exemplary embodiment of the vertical decimation unit of FIG.

FIG. 18 is a signal waveform diagram of each part of FIG. 17. FIG.

19 is an exemplary view of one embodiment of the horizontal decimation unit of FIG.

FIG. 20 is a signal waveform diagram of each part of FIG. 19. FIG.

21 is another exemplary embodiment of the horizontal decimation unit of FIG.

FIG. 22 is a signal waveform diagram of each part of FIG.

23A is a detailed block diagram of the first frame rate converter;

FIG. 23B is a signal waveform diagram of each part of FIG. 23A. FIG.

FIG. 24 is a detailed configuration diagram of the display processor of FIG.

* Explanation of symbols for main parts of the drawings

1 input terminal 2 decoding unit

3: sequential scan conversion unit 4: frame rate conversion unit

5, 8, 12: switching unit 6, 9: vertical decimation unit

7, 10: horizontal decimation unit 11: switching selection control unit

13 frame rate conversion unit 14 display processing unit

The present invention relates to a receiver for digital high definition television (HDTV) and a method for converting an HDTV video format. In particular, the present invention relates to an HDTV receiver when the transmitted video format is one of several formats and the decimation format is 525-line progressive scan. And an HDTV video format conversion method.

HDTV standards in the US are designed to encode and decode a variety of images without restricting the video format to a single one. As a result, the frame rate is 60㎐ and the 1050 line is sequential scan. It is known that six formats with frame rates of 24㎐, 30㎐, and 60㎐ are possible with sequential scanning of 787.5 lines. In this case, the frame rate of 24㎐ and 30 필름 is taken into account in the film mode (film ㅡ ㄷ ㄷ). In case of transmitting a movie frame, it is efficient in many ways to transmit the frame rate to 24㎐, 30㎐ in sequential formula. to be.

The images that can be transmitted in this way vary, but in general, the image standard displayed on the monitor will be limited to one to suit the characteristics of the monitor. Therefore, even if any of the above six image formats are input, a device for decoding the image and converting it to a display format and displaying it on a monitor is essential for an HDTV receiver.

In addition, a 30-inch monitor displays the above-described HDTV image, but ordinary viewers do not notice much difference even when decimating a lower resolution (eg, 525-line sequential scan) image.

Accordingly, an object of the present invention is to provide an HDTV receiver and an HDTV video format converting method for decoding and displaying a video format on a monitor when the video format is fixed to 525-line progressive scan. .

The HDTV receiver of the present invention for achieving the above object comprises: decoding means for reconstructing a compressed bitstream into a video signal, and sequentially converting the compressed bitstream into a sequential scan format when the video signal output from the decoding means is an interlaced scan format. Scanning conversion means, first frame rate conversion means for converting the frame rate to 30 Hz when the video signal output from the decoding means is not 30 Hz, the decoding means, sequential scanning conversion means, and first First switching means for selecting one of the video signals output from the frame rate converting means and outputting an image signal having a frame rate of 30 Hz in a 1050-line sequential scanning format; an image output from the decoding means and the first frame rate converting means Second switching means for selecting one of the signals and outputting an image signal having a frame rate of 30 Hz in a 787.5-line sequential scanning format; First vertical decimation means for converting lines per frame of the video signal output from said first switching means, second vertical decimation means for converting lines per frame of the video signal output from said second switching means; Horizontal decimation means for converting the number of pixels per line of the signal output from the vertical decimation means, second horizontal decimation means for converting the number of pixels per line of the signal output from the second vertical decimation means, and the first A third switching means for selecting one of the video signals output from the first and second horizontal decimation means and outputting an image signal having a frame rate of 30 Hz in a 525-line sequential scanning format; A frame rate converting means for converting a frame rate of 60 Hz, and displaying a video signal output from the fraudulent second frame rate converting means. Generates a selection signal from the display processing means and the input bit stream to convert to is characterized in that the selection consists of a switching control means for controlling said first, second and third switching means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of an HDTV receiver having a 525-line progressive scan monitor display image format according to the present invention, where 1 is an input terminal, 2 is a decoding unit, 3 is a sequential scan conversion unit, 4 is a frame rate conversion unit, and 5 , 8 and 12 are switching units, 6 and 9 are vertical decimation units, 7 and 10 are horizontal decimation units, 11 is a switching selection control unit, 13 is a frame rate conversion unit, and 14 is a display processing unit. .

An HDTV receiver having a 525-line progressive scan monitor display image format according to the present invention is sequentially provided to a decoding unit 2 which decodes a compressed bitstream when it is input through the input terminal 1 as shown in FIG. The scanning converter 3 and the frame rate converter 4 are connected to each other, and the switching unit 5 is connected to the decoding unit 2, the sequential scan converter 3, and the frame rate converter 4. The switching unit 8 is connected to the decoding unit 2 and the frame rate converter 4, and the vertical decimation units 6 and 9 are connected to the switching units 5 and 8, respectively. The horizontal decimations 7 and 10 are connected to the vertical decimation parts 6 and 9, respectively, and the switching part 12 is connected to the horizontal decimation parts 7 and 10, and to the switching part 12. A frame rate converter (13), a display processor (14) to the frame rate converter (13), and the compressed bitstream input terminal (1) The configuration to connect the select switching control section 11 to the switching unit (5, 8, 12).

The decoding unit 5 restores the bitstream input through the input terminal 1 to a video signal, and the sequential scanning converter 3 intercepts the video signal output from the decoding unit 2 by 1050 lines. In the case of the scan type, the frame rate is converted into a progressive scan format having a frame rate of 30 ms. The frame rate converter 4 converts the frame rate to 30 ms when the frame rate of the output image of the decoder 2 is not 30 ms. Do it.

The switching unit 5 selects an output of the decoding unit 2 when the input image is a 1050-line progressive scan format and the frame rate is 30 Hz, and converts the progressive scan when the 1050-line interlaced scanning format is used. The output of the subsection 3 is selected, and when the 1050-line progressive scan format and the frame rate is 24 ms, the output of the frame rate converter 4 is selected.

The switching unit 8 selects the output of the frame rate converter 4 when the output image of the decoding unit 2 is a 787.5-line sequential scan format and the frame rate is 60 Hz or 24 Hz. If the frame rate is 30 ms in the scan format, the output of the decoding section 2 is selected.

The vertical decimation section 6 and the horizontal decimation section 7 convert the video format of 1050 lines outputted from the switching section 6 into a video format of 525 lines. The vertical decimation unit 9 and the horizontal decimation unit 10 convert the image format of 787.5 lines output from the switching unit 8 into an image format of 525 lines.

The switching unit 12 selects one of the output images of the horizontal decimation units 7 and 10, and the frame rate conversion unit 13 converts the frame rate of 30 Hz to 60 Hz, and displays the display. The processor 14 interpolates the color difference signal, converts Y, U, and V into R, G, and B (red green blue), and outputs the result to the monitor.

The switching selection controller 11 controls the switching units 5, 8, and 10 by generating a control signal from an input compressed bitstream.

2 is a diagram showing selection criteria of each switching unit 5, 8, 12 according to the present invention.

How each of the switching unit 5, 8, 12 is switched according to the input image as shown in Figure 2, the switching unit (5, 8, 12) can be implemented as a multiplexer.

FIG. 3A is a detailed configuration diagram of the switching selection control unit 11 of FIG. 1, and FIG. 3B is a control reference display diagram of selection operation of FIG. 3A, 15 is an input image classification unit, AND is an AND gate, and N is an inverter. .

As shown in FIG. 3A, the switching selection controller 11 interlaces six inputtable images from the input terminal 1 in a sequential and progressive scan format, 1050 lines and 787.5 lines per frame, and a frame rate of 30 Hz. And an input image classifying unit 15 which is classified into three other signals, an interlaced and progressive scanning format display signal output terminal of the input image classifying unit 15, and a signal output terminal having a frame rate of 30 Hz and the like. An AND gate is connected, and an inverter N is connected to the interlaced and progressive scan format display signal output terminal.

Referring to Figure 3b will be described the operation of the switching selection control unit 11 as follows.

The six inputtable video signals are classified into three display signals by the switching selection controller 11 to generate the selection control signals SO, S1 and S2 of the respective switching units 5, 8, and 12.

The selection control signal SO of the switching unit 5 is a combination of a signal indicating a frame rate and a signal indicating whether an input is interlaced or sequential scanning to the output of the AND gate AND and the inverter N. Is done.

The selection control signal S1 of the switching unit 8 becomes a signal indicating a frame rate, and the selection control signal S2 of the switching unit 12 indicates whether a line per frame of the input is in a 1050 line format or a 787.5 line format. It becomes a signal to indicate.

That is, the switching unit 5, 8, 12 receives a signal indicating the interlaced and progressive scan format, the line per frame, and the frame rate as a bitstream input from the input terminal 1, and has a frame rate of 30 Hz. After converting to progressive scan format, the frame format is converted to 525-line format, and then converted to a frame rate of 60 Hz for display on a monitor.

4a is a detailed configuration diagram of the decoding unit 2 of FIG. Discrete Cosine Transform), 19 is an adder, 20 is a slice buffer, 21 is a frame memory, and 22 is a motion compensator.

The decoding unit 2 connects the inverse quantization unit 17 to the VLD and demultiplexing unit 16 as shown in FIG. 4A, and connects the IDCT 18 to the inverse quantization unit 17. An adder 19 is connected to the IDCT 18, a frame memory 21 and a slice buffer 20 are connected to the adder 19, and the frame memory 21, a VLD, and a demultiplexer are connected to the IDCT 18. 16) is configured by connecting the motion compensation unit 22.

The compressed bitstream coming from the input terminal 1 is first converted into a meaningful signal by the VLD and demultiplexer 16, and then the motion compensator 22 is used as motion information output from the VLD and demultiplexer 16. ) And outputs to the adder 9.

The output signal of the VLD and demultiplexing unit 16 is processed through the inverse quantization unit 17 and the IDCT 18 and output from the motion compensating unit 22 and the adder 19. Is added in block unit, and the output block unit signal is stored in the slice buffer 20 for output in line units, and then the sequential scan conversion unit 3 and frame rate conversion unit 4 in line units. ), And to the switching units 5 and 8.

In this case, the macroblock type signal and motion information output from the VLD and the demultiplexing unit 16, and the signal output from the IDCT 8 are used for the sequential scanning in preparation for the case where the sequential scanning conversion unit 3 is used. It is sent to the expression conversion unit 3.

The signal to be decoded is represented in basic units of frames, macroblocks, and slices, as shown in FIG. 4B.

FIG. 5 is a detailed block diagram showing an embodiment of the sequential scan conversion unit 3 of FIG. 1, FIG. 6 is a signal waveform diagram of each part of FIG. 5, 23 is a signal input terminal, 24 is a line delay unit, 26 represents an adder, 27 represents a divider, and 28 represents a multiplexer.

According to an exemplary embodiment of the sequential scan converter 3, the line delay unit 24 is input to an input terminal 23 to which a signal having a frame rate of 60 Hz is input in a 1050-line interlaced scan format as shown in FIG. And a line delay unit 25 connected to the line delay unit 24, and an input terminal 1 of a signal having a frame rate of 30 Hz in the 1050 line interlaced scanning format with the line delay unit 25. Connected to the adder 26 and the divider 27 to the adder 26, and connected to the multiplexer 28 to the line delay unit 24 and the divider 27 is not scanned The line is interpolated with the average above and below and output to the switching unit 5.

A signal having a frame rate of 60 Hz in the 1050-line interlaced scan format input from the decoding unit 2 is delayed through the line delay units 24 and 25, and then further added to the delayed signal through the adder 26. Then, 1/2 is divided by the divider 27 and output to the multiplexer 28.

The multiplexer 28 selects the divided signal and the output signal of the line delay unit 24 and outputs the same to the switching unit 5.

Assuming that the output of the decoding unit 2 is made in units of frames, the output of the decoding unit 2 is input in units of frames in an interlaced scan format, so one field (Even or Odd) of the two fields is discarded and the other field is discarded. Only used is converted to progressive scan format, and the frame rate is converted to 30Hz for possible hardware implementation.

In this case, the line delay units 24 and 25 and the adder 26 are used to interpolate the unscanned lines, and the multiplexer 28 is used to alternately select the scanned lines and the interpolated lines.

The signal waveform showing the detailed operation of the sequential scan conversion section 3 configured as described above is as shown in FIG.

FIG. 7 is a detailed block diagram showing another embodiment of the sequential scanning converter 3 of FIG. 1, FIG. 8 is a signal waveform diagram of each part of FIG. 7, 29 is a signal input terminal 30, 31 is a line delay unit, 32 Is an adder, 33 is a 1/2 divider, 34 and 35 are multiplexers, and 36 is a moving part and a stop part discriminating part.

Another embodiment of the sequential scan converter 3 connects the line delay unit 31 to the line delay unit 30 to which a signal is input from the decoding unit 2, as shown in FIG. An adder 32 is connected to the line delay unit 31 and an input terminal 29 of a signal having a frame rate of 60 Hz in a 1050-line interlaced scanning format, and a 1/2 divider 33 to the adder 32. Connect the multiplexer 34 to the line delay unit 30 and the 1/2 divider 33, and connect the multiplexer 35 to the multiplexer 34 and the line delay unit 30. In addition, the multiplexer 34 is configured to connect a moving unit and a stop unit discrimination unit 36 which receive the macro block type, error, and motion information from the decoding unit 2.

The line delay units 30 and 31 operate the adder 3, the 1/2 divider 33, and the multiplexer 35 in the same manner as the sequential scan converter 3 of FIG. 6. And the stopper determiner 36 receives a signal such as a macro block type, an error, and motion information from the decoder 2, and divides an area into stops and a mover. Interpolation, and the selection of the multiplexer 34 is controlled to increase the resolution of the stop by interpolating the average value between lines in the case of a moving part.

That is, the multiplexer 34 outputs the output signal of the moving part and the stop part discriminating part 36 among the outputs of the line dividing part 30 of the field different from the output of the 1/2 division period 33 which is the average between lines. The multiplexer 35 selects the scanned lines and the interpolated lines alternately per line.

The signal waveform showing the detailed operation of the sequential scan conversion section 3 configured as described above is as shown in FIG.

FIG. 9 is a detailed configuration diagram of the frame rate converter 4 of FIG. 1, FIG. 10 is a signal waveform of each part of FIG. 9, 37 is a signal input terminal, 38, 40. 42 is a memory, 39, 41 is a multiplexer, 43 denotes a memory control unit, respectively.

As shown in FIG. 9, the frame rate converter 4 stores input signals whose frame rate is not 30 [mu] s, respectively, and connects the memory controller 43 to the memories 38, 40, and 42. The multiplexer 41 is connected to the plurality of switches 40 and 42, and the multiplexer 39 is connected to the multiplexer 41 and the memory 38 so that the frame unit 30 has a frame rate of 30 Hz. Output the signal.

When a signal having a frame rate of 60 Hz is input, the memory controller 43 controls the memory 38 to perform a write operation while skipping by one frame, and to continuously read at an output speed.

In addition, when the frame rate is 24 ms, the memory controller 43 uses the two memories 40 and 42 to divide the input into four frame units in the first memory 40 to store only the first frame, and then to read the second multiplexer ( 42, the controller continuously writes an input, reads the first frame from the first memory 40, and immediately reads four frames at the output speed, while the second memory 42 continues to write and stop reading.

The signal waveform representing the operation of the frame rate converter 4 is as shown in FIG.

FIG. 11 is a detailed configuration diagram of the vertical decimation unit 6 of FIG. 1, FIG. 12 is a signal waveform diagram of each part of FIG. 11, 44 is a signal input terminal, 45 is a line delay unit, 46 is a multiplier, 47 is an adder, 48 denotes a memory, 49 denotes a memory control unit, and 50 denotes a filter unit.

The vertical decimation unit 6 converts the number of lines per frame in a ratio of 2: 1, and the filter unit 50 and the filter unit 50 for eliminating aliasing as shown in FIG. Memory 48 for converting the output of the data into an output format, and a memory controller 49 for controlling the memory 48.

The memory 48 is written while skipping line by line under the control of the memory controller 49 and read at the output speed.

The filter unit 50 passes a video signal having a frame rate of 30 [mu] s through a plurality of line delay units 45 in a 1050-line sequential display format input from the switching unit 5, and the video signal and line delay. Each signal passing through the unit 45 is passed through a multiplier 46 having respective coefficients K1, K2, ..., Kn, and the signals passed through the plurality of multipliers 46 are then added to the plurality of adders 47. ), And output to the memory 48.

In this case, when the coefficients K1, K2, ..., Kn of the filter unit 50 are two (K1, K2), that is, outputted as an average between lines using one line delay unit 45, hardware implementation is simple. However, optimizing can occur.

The signal waveform indicating the operation of the 2: 1 vertical decimation section 7 is as shown in FIG.

FIG. 13 is a detailed configuration diagram of the horizontal decimation unit 7 of FIG. 1, FIG. 14 is a signal waveform diagram of each part of FIG. 13, 51 is a signal input terminal, 52 is a coefficient input terminal, 53 is a latch, 54 is a multiplier, 55 Denotes an adder, 56 denotes a latch, and 57 denotes a peter portion.

The horizontal decimation unit 7 converts the number of pixels per line in a ratio of 2: 1, and is connected to the filter unit 57 and the filter unit 57 to remove the freezing as shown in FIG. And latches 56 for latching signals by skipping pixel by pixel.

The filter unit 57 passes image signals input from the vertical decimation unit 6 through a plurality of latches 53, and multiplies a plurality of multipliers of the image signals and the respective signals passed through the latch 53. And pass through the plurality of multipliers 54, and output through the plurality of adders 55 to output to the latch 56, the coefficients of the filter section 57, respectively. If (K1, K2, ..., Kn) are two (K1, K2), that is, outputting as an average between pixels using one latch 53 may result in arising.

The latch 56 latches the video signal output from the filter unit 57 by one pixel, and the signal waveform representing the operation is as shown in FIG.

FIG. 15 is a configuration diagram showing one embodiment of the vertical decimation unit 9 of FIG. 1, FIG. 16 is a signal waveform diagram of each part of FIG. 15, 58 is a signal input terminal, 59 is a coefficient input terminal, and 60 is a line delay unit. Denotes a multiplier, 62 denotes an adder, 63 denotes a memory, 64 denotes a memory control unit, and 65 denotes a filter unit.

One embodiment of the vertical decimation unit 9 is to convert the number of lines per frame in a 3: 2 ratio, and as shown in FIG. 15, the filter unit 69 and the filter unit for removing the freezing. The memory 63 connected to the memory 65 and the memory controller 64 controls to store only two lines in the memory 63 while discarding one line in units of three lines from the output of the filter unit 65.

The filter unit 65 passes an image signal having a frame rate of 30 Hz and the image signal through a plurality of line delay units 60 in a 787.5-line sequential scanning format inputted to the switching unit 8, The video signal and each signal passed through the line delay unit 60 are passed through a plurality of multipliers 61, and the signals passing through the plurality of multipliers 61 are added through a plurality of adders 62. And output to the memory 63.

In this case, when the coefficients K1, K2, ..., Kn of the filter unit 65 are two (K1, K2), that is, outputted as an average between lines using one line delay unit 60, the hardware implementation Simple but optimizing can occur.

The signal waveform representing the operation of the vertical decimation section 9 configured as described above is as shown in FIG.

FIG. 17 is a detailed configuration diagram of the vertical decimation unit 9 of FIG. 1, and FIG. 18 is a signal waveform diagram of each part of FIG. 17, 66 is an input terminal, 67 is a line delay unit, 68 is an adder, and 69 is 1/2. A divider, 70 denotes a multiplexer, 71 denotes a memory, and 72 denotes a memory controller.

Another embodiment of the vertical decimation section 9 converts the number of lines per frame at a 3: 2 ratio, as shown in FIG. 17, from the switching section 8 to a 787.5-line sequential scan format. The adder 68 is connected to the line delay unit 67 to which the 30 kHz video signal is input and the video signal input terminal 66, and the 1/2 divider 69 is connected to the adder 68. The multiplexer 70 is connected to the 1/2 divider 69 and the image signal input terminal 66, the memory 71 is connected to the multiplexer 70, and the memory controller 72 is connected to the memory 71. To configure.

An average is obtained using the line delay unit 67, the adder 68, and the divider 69, the average line and the first input line are selected by the multiplexer 70, and the required two lines are output from the multiplexer. Only the memory 71 is stored and read.

That is, the first output line interpolates to the first input line and the second output line interpolates to the average of the second and third lines of the input.

The signal waveform showing the operation of the vertical decimation section 9 configured as described above is as shown in FIG.

19 is a block diagram showing an embodiment of the first horizontal decimation unit 10, FIG. 20 is a signal waveform diagram of each part of FIG. 19, 73 is a filter unit, 74 is a coefficient input stage, 75 is a multiplier, 76 Silver latch, 77 is an adder, 78 is a 1: 3 demultiplexer, and 79 is a 2: 1 multiplexer.

As shown in FIG. 19, the horizontal decimation unit 10 converts the number of pixels per line at a 3: 2 ratio, and the filter unit 73 and the filter unit for eliminating the aging. 73) and an output configured with a 1: 3 demultiplexer 78 and a 2: 1 multiplexer 79.

The filter unit 73 passes image signals input from the vertical decimation unit 9 through a plurality of latches 76, and a plurality of multipliers of the image signals and the respective signals passed through the latch 6. And pass through the multipliers 75, respectively, and pass through the plurality of multipliers 77 to output to the 1: 3 demultiplexer 78 and the coefficients K1 and K2. In the case of two (K1, K2), that is, outputting as an average between pixels using one latch 76, aligning may occur.

The 1: 3 demultiplexer 78 represents the output of the filter unit 73 as three phases, discards one of the phases, and inputs only two phases to the 2: 1 multiplexer 79 to provide a desired output. Get

The signal waveform representing the operation of the horizontal decimation section 10 configured as described above is as shown in FIG.

FIG. 21 is a block diagram showing another embodiment of the horizontal decimation unit 10 of FIG. 1, FIG. 22 is a signal waveform diagram of each part of FIG. 21, 80 is an input terminal, 81 is a latch, 82 is an adder, and 83 is 1 / 2 divider, 84 denotes a multiplexer, 85 denotes a 1: 3 demultiplexer, and 86 denotes a 2: 1 multiplexer.

Another embodiment of the horizontal decimation section 10 converts the number of pixels per line in a 3: 2 ratio, as shown in FIG. 21, and a latch into which a video signal is input from the vertical decimation section 9. An adder 82 is connected to the 81 and the video signal input terminal 80, a 1/2 divider 83 is connected to the adder 82, and the 1/2 divider 83 and the video signal are connected to the adder 82. A multiplexer 84 is connected to the input terminal 80, a 1: 3 demultiplexer 85 is connected to the multiplexer 84, and a 2: 1 multiplexer 86 is connected to the 1: 3 multiplexer 85. do.

The average between pixels is obtained using the latch 81, the adder 82, and the 1/2 divider 83, the average pixel value and the first input pixel are selected by the multiplexer 84, and the selected value is selected. The 1: 3 demultiplexer 85 divides the three phases, discards one of them, and sends only two phases to the 2: 1 multiplexer 86 to select the desired output.

That is, the input pixel is divided into three pixel units, the first pixel is output as it is, and the second output pixel is interpolated by the average of the second and third inputs.

The signal waveform showing the operation of the horizontal decimation section 10 configured as described above is as shown in FIG.

FIG. 23A is a detailed configuration diagram of the frame rate converter 13 of FIG. 1, FIG. 23B is a signal waveform diagram of each part of FIG. 23A, 87 is an input terminal, and 88 is a frame memory.

The frame rate converter 13 is a 525-line sequential scan format for converting an image signal having a frame rate of 30 Hz to twice the frame rate to 60 Hz. As shown in FIG. 23A, the frame memory 88 The signal waveform representing the operation is shown in FIG. 23B.

That is, the video signal is stored in the frame memory 88 and read at a double speed to double the frame rate.

24 is a detailed configuration diagram of the display processor 14 of FIG. 1, where 89 is a color difference signal interpolation unit, and 90 is a conversion unit from Y, U, V to R, G, and B (red green blue), respectively.

As shown in FIG. 24, the display processor 14 converts the final Y, U, and V signals into R, G, and B signals, which are color signals, to the color difference signal interpolator 89 for interpolating the color difference signals. , V is configured by connecting the conversion unit 90 from R, G, B.

The present invention, which is configured and operated as described above, is a US-based HDTV receiver, when the size of the monitor screen is small, rather than displaying an image having the full resolution of the HDTV, converting the image into a 525-line sequential scan type and displaying the image on the monitor. There is an application effect to increase the.

Claims (18)

Decoding means (2) for reconstructing the compressed bitstream into a video signal, sequential scan conversion means (3) for converting the video signal output from the decoding means (2) into a progressive scan format, and the decoding A first frame rate converting means 4, said decoding means 2, and a sequential scan type converting means 3 for converting the frame rate to 30 [mu] s when the video signal output from the means 3 is not 30 [mu] s. First switching means (5) for selecting one of the video signals output from the first frame rate converting means (4) and outputting a video signal having a frame rate of 30 Hz in a 1050-line progressive scan format; Second switching means (8) for selecting one of the video signals output from (2) and the first frame rate converting means (4) to output an image signal having a frame rate of 30 Hz in a 787.5-line sequential scanning format; 1 output from the switching means (5) First vertical decimation means (6) for converting the number of lines per frame of the video signal, and second vertical decimation means (9) for converting the number of lines per frame of the video signal output from the second switching means (8). Horizontal decimation means (7) for converting the number of pixels per line of the signal output from the first vertical decimation means (6), and the number of pixels per line of the signal output from the second vertical decimation means (6). Selects one of the video signals output from the second horizontal decimation means (10) and the first and second horizontal decimation means (7, 10), and converts the frame rate into a 525-line sequential scan format. Third switching means 12 for outputting a video signal, second frame rate converting means 13 for converting a frame rate of the video signal output from the third switching means 12 by 60 Hz, and the second frame rate conversion. The video signal output from the means 13 is decoded. Display processing means 14 for converting to play, and switching selection control for generating the selection signal from the input bitstream to control the first, second, and third switching means 5, 8, 12 Etched buoy (HDTV) receiver having a 525-line progressive scan monitor display image format, characterized in that it comprises a means (11). 2. The input image classification means (15) according to claim 1, wherein the switching selection adjusting means (11) classifies the input image stream from the input bitstream into signals representing interlaced and progressive scan formats, lines per frame, and frame rates. The AND and OR of the interlaced and progressive scan format output from the image classification means 15 and the signal representing the frame rate, and the interlaced and the progressive scan format output from the input image classification means 15. An HDTV receiver having a 525-line progressive scan monitor display image format, comprising an inverter N for inverting a signal to be displayed. 2. The apparatus of claim 1, wherein said decoding means (2) outputs from a variable length decoder (VLD) and demultiplexing means (16) and said VLD and demultiplexing means (16) for converting said compressed bitstream into a meaningful signal. Compensating the motion information output from the dequantization means 17, the IDCT means 18 to which the signal output from the dequantization means 17, the VLD and the demultiplexing means 16 are input. A motion compensator 22, an adder 19 to which a signal output from the IDCT 18 and a signal output from the motion compensator 22 are added, and an output signal of the adder 19; An etchive having a 525-line sequential scan type monitor display image format, comprising frame memory means 21 for outputting to the motion compensation means 22 and slice buffer means 20 (HD). TV) receiver. The method of claim 1, wherein the sequential scan converting means (3) comprises a first line delay means (24) for inputting an image signal in interlaced scan format, and a second connected to an output terminal of the first line delay means (24). An adder means 26 and a divider means 27 for interpolating an unscanned line by averaging a line delay means 25, an image signal in the interlaced scan format and an output signal of the second line delay means 25, And a multiplexer 28 alternately selecting the interpolated lines output from the dividing means 27 and the scanned lines output from the first line delay means 24. An HDTV receiver having a scan monitor display image format. The method according to claim 1, wherein the progressive scan converting means (3) comprises a first line delay means (30) for inputting an image signal in an interlaced scan format, and an output signal of the first line delay means (30) as an input. An adder 32 and a divider means for interpolating the unscanned lines by averaging the second line delay means 31, the output signal of the second line delay means 31 and an image signal in an interlaced scan format; 33) a moving part and a stop part discriminating means 36 for distinguishing a stop part and a moving part from the input image signal and outputting a control signal, and an interpolated line output from the dividing means 33 and the first line delay. A first multiplexer 34 for selecting a "scanned" line output from the means 30 according to a control signal output from the moving part and the stop part discriminating means 36, and a signal output from the first multiplexer And from the first line delay means 30 Chulryeo second multiplexer (35) 525 TV lines chidi (HDCV) having a receiving device for the progressive scanning type of monitor display picture format, characterized in that consisting of selecting alternating signal. The first frame means (4) according to claim 1, wherein the first frame rate converting means (4) stores the first memory means (38) by skipping frame by frame when a video signal having a frame rate of 60 Hz is input, and an image having a frame rate of 24 Hz. A first signal for selecting from among second and third memory means 40 and 42 and video signals output from the second and third memory means 40 and 42, which are divided into four frames and repeat a read and write operation when a signal is input. A second multiplexer 38 for selecting among a multiplexer 41, an image signal output from the first multiplexer 41 and an image signal output from the first memory means 38, and the first, second, and Receiving an HDTV having a 525-line progressive scan monitor display image format, comprising memory control means 43 for controlling read and write operations of the third memory means 38, 40, 42. Device. 2. An HDTV reception according to claim 1, characterized in that said first, second and third switching means (5, 8, 12) comprise a multiplexer. Device. 2. The apparatus of claim 1, wherein the first vertical decimation means (6) comprises: a filter means (50) for eliminating the aging, a memory means (48) for converting the output of the filter means (50) to an output format, and An etchive having a 525-line sequential scan type monitor display image format, characterized by comprising memory control means 49 which controls the memory means 48 to perform a read and write operation while skipping line by line. HDTV) receiver. 2. The first horizontal decimation means (7) according to claim 1, wherein the first horizontal decimation means (7) includes a filter means (57) for eliminating an aging, and a first latch (56) for outputting the output of the filter means (57) by skipping a single pixel. An etch receiver (HDTV) receiver having a 525-line progressive scan monitor display image format. 2. The second vertical decimation means (9) according to claim 1, characterized in that the second vertical decimation means (9) comprises: a filter means (65) for eliminating the aging, a memory means (63) for storing the output of the filter means (65), and the filter means. Echidi having a 525-line sequential scan type monitor display image format, characterized by comprising memory control means 64 controlling to store only two lines in the multiplexer means 63 in units of three lines of the output of 65. TV (HDTV) receiver. 2. The second vertical decimation means (9) further comprises: line delay means (67) and line delay means (67) for inputting a video signal having a frame rate of 30 [mu] s in a 787.5-line progressive scan format; An addition signal 68 and a distributing means 69 for generating an average of an image signal having a frame rate of 30 Hz in a 787.5-line sequential scanning format and a frame rate of 30 Hz in a 787.5-line sequential scanning format. A multiplexer for selecting an image signal and an output signal of the division means 69, memory means 17 for storing and reading the output of the multiplexer 70, and controlling the memory 71 to perform read and write operations And an 525-line progressive scan monitor display image format comprising a memory control means (72). 2. The second horizontal decimation means (10) according to claim 1, wherein the second horizontal decimation means (10) divides the output of the filter means (73) and the filter means (73) into three phases and eliminates only two phases. A 525 line progressive scan monitor display image format comprising: a 1: 3 demultiplexer 78, and a 2: 1 multiplexer 79 for selecting and outputting the output of the 1: 3 decimation 78. HDTV receiver. 2. The second horizontal decimation means (10) according to claim 1, wherein the second horizontal decimation means (10) comprises: a latch (81) to which a video signal is input, an addition means (82) for making an average of the output signal and the video signal of the latch (81); By dividing the output of the fractional end 83, the first multiplexer 84 for selecting the video signal and the divider 83, and the output of the first multiplexer 84 into three phases, only two phases are selected. A 525-line progressive scan monitor display image format comprising a 1: 3 demultiplexer 85 for output and a second multiplexer 86 for selecting and outputting the output of the 1: 3 demultiplexer 85. CDTV receiver. 2. The 525-line progressive scan monitor display image format according to claim 1, characterized in that the second frame rate converting means (13) comprises a frame memory (88) for storing image signals and reading them at twice the speed. Echidition (HDTV) receiver having a. 2. The display processing means according to claim 1, wherein the display processing means (14) is a color difference signal interpolation means (89) for interpolating a color difference signal, and R, G, B conversion for converting Y, U, V signals to R, G, and B signals. Etched receiver (HDTV) receiver having a 525-line progressive scan monitor display image format, characterized in that it comprises means (90). 11. The filter according to claim 8 or 10, wherein the filter means (50, 65) are connected to a plurality of line delay means (45, 60), image signals and output signals of the plurality of line delay means (45, 61) connected in series. 525-line sequential scanning formula comprising a multiplier (46, 61) to multiply coefficients (K1, K2, ..., Kn), and adders (47, 62) to add the output of the multiplier (46, 61) An HDTV receiver having a monitor display picture format. 13. The filter means (57, 73) according to claim 9 or 12, wherein the filter means (57, 73) comprises a plurality of latches (53, 76) connected in series, the image signal and the output signal of the plurality of latches (53, 76) coefficient (K1, 525-line progressive scan monitor display image format comprising a multiplier (54, 75) for multiplying K1, ..., Kn) and adders (55, 77) for adding up the outputs of the multiplier (54, 75). Echidition (HDTV) receiver having a. A decoding step of reconstructing the compressed bitstream into a video signal, a sequential scanning conversion step of converting the video signal output from the decoding step into a sequential scanning format, and a frame rate of the video signal output from the decoding step If the frame rate is not 30 ms, one of the first frame rate converting step of converting the frame rate to 30 ms and the video signal output from the decoding step sequential scan converting step and the first frame rate converting step are selected into a progressive scan format. A signal selecting step of outputting a video signal having a frame rate of 30 Hz, a scanning line converting step of converting lines per frame of the video signal output from the signal selecting step into 636 scanning lines, and outputting from the scanning line converting step A pixel number converting step of converting pixels per line of the signal to be output, and an image scene output from the pixel number converting step HDTV video format conversion method, characterized in that configured by comprising a frame rate of the second frame conversion step of converting a 60㎐.