KR960013648B1 - Hdtv receiver - Google Patents

Abstract

a decoding means(2) decoding HDTV image signal; a control means outputting the control signal according to the frame ratio and the number of the scan line of the image format; a frame ratio transforming means(3) transforming the frame ratio of the signal outputted from the decoding means(2) into the NTSC frame ratio; plural decimation means(13) decimating the number of the scan line according to the control signal of the control means a mode converting means(1) converting the signal from the decimation means(13) into a display mode; and a display processing means(11) processing the signal to display in a monitor.

Description

HTV receiver

1 is a detailed configuration diagram of a decoder of the HDTV receiver of the present invention.

2 is a (a) (b) (c) (d) is a state diagram of the display mode according to the present invention.

3 is a block diagram of an HDTV receiver according to the present invention.

4 is a detailed configuration diagram of the frame converter of FIG.

5 is a signal waveform diagram of each part of FIG.

6 is a detailed block diagram of the 2: 1 decimation unit of FIG.

7 is a signal waveform diagram of each part of the 2: 1 vertical decimation part of FIG.

8 is a signal waveform diagram of each part of the 2: 1 horizontal decimation part of FIG.

9 is a detailed block diagram of the 3: 2 decimation unit of FIG.

FIG. 10 is a signal waveform diagram of each part of the 3: 2 vertical decimation part of FIG.

FIG. 11 is a signal waveform diagram of each part of the 3: 2 horizontal decimation part of FIG.

12 is a detailed configuration diagram of the NTSC conversion unit I of FIG.

13 is a detailed configuration diagram of the NTSC conversion unit II of FIG.

14 is a signal waveform diagram of each part of FIG.

FIG. 15 is a detailed configuration diagram of the NTSC converter III of FIG.

* Explanation of symbols for main parts of the drawings

1: mode converter 2: decoder

3: frame rate converter 4, 7, 10, 25, 27, 40, 46, 48: multiplexer

5: 2: 1 decimation part 6: 3: 2 decimation part

8: NTSC converter I 9: NTSC converter II

11: display processing unit 12: multiplexer selection control unit

13: decimation unit 14: VLD and demultiplexer

15: dequantization unit 16: IDCT unit

17,38,44: Adder 18: Slice buffer

19,56: frame memory 20: motion compensator

21: NTSC converter III 22, 23, 24, 31, 41, 51: memory

26, 32, 42, 52, 57: Memory control unit 28: 2: 1 vertical decimation unit

29,37: Line delay 30,34: Filter part

33,35,43: Latch 36: 2: 1 Horizontal decimation part

39,45: 1/2 divider 47: Demultiplexer

49: 3: 2 vertical decimator 50: 3: 2 horizontal decimator

53: K: L Horizontal decimation unit 54,58: 1: K demultiplexer

55,59: L: I multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an HDTV receiver, and more particularly to an HDTV receiver that can be displayed on an existing TV in various modes when the transmitted video format is one of several formats.

In the US, the HDTV standard is designed to encode and decode a variety of images without limiting the video format to a single one. As a result, the frame rate is 60Hz, 1050 lines and the frame rate is 24Hz, 30Hz, and 787.5 lines. It is known that a total of six formats are available with a scan rate of 24 Hz, 30 Hz, and 60 Hz.

In this case, the frame rate is 24Hz, 30Hz considering the film mode (Film Mode), because the transmission of the frame rate to 24Hz and 30Hz sequential scanning in the case of transmitting the movie film is efficient in many ways.

While the images that can be transmitted in this way vary, generally, the image standard displayed on the monitor will be limited to one to suit the characteristics of the monitor.

Therefore, a device that decodes any of the six video formats and converts it to a display format and displays it on a monitor is essential for an HDTV receiver, and the HDTV receiver is compatible to watch HDTV broadcasts through a conventional TV. You also need a device.

Accordingly, an object of the present invention is to provide an HDTV receiver that is compatible to display on a conventional TV in various modes when the transmitted video format is one of several formats.

In order to achieve the above object, the present invention includes decoding means for reconstructing an HDTV (HDTV) video signal input to any one of a plurality of video formats; Control means for outputting a control signal in accordance with the frame rate of the input video format and the scanning player; Frame rate converting means for converting the frame rate of the signal output from the decoding means into a frame rate of NTSC standard according to the control signal; And a plurality of decimation units for converting a scan player of the signal output from the frame rate converting unit into a NTSC standard scan player according to the type of HDTV video format. Decimation means for decimating according to a control signal; Mode conversion means for converting the signal output from the decimation means into a desired display mode; And display processing means for processing the signal output from the mode converting means to be displayed on the monitor.

Hereinafter, a preferred embodiment of an HDTV receiver according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a detailed configuration diagram of a decoder applied to an HDTV receiver according to the present invention.

The decoder 2 includes a variable length decoder (VLD) and demultiplexer 14, an inverse quantizer 15, an inverse discrete cosine transform (IDCT) unit 16, an adder 17, as shown in FIG. It is composed of a frame memory 19, a slice buffer 18, and a motion compensator 20.

The VLD and demultiplexer 14 decodes and classifies the compressed bitstream into meaningful signals, that is, motion information, macroblock types, coefficients, and quantization step sizes.

The dequantization unit 15 performs nutrition by using signals output from the VLD and the demultiplexer 14, and the IDCT unit 16 performs IDCT processing on the output signal of the dequantization unit 15.

The motion compensator 20 compensates for the motion by using the motion information output from the VLD and the demultiplexer 14 and stores the motion compensated signal in the frame memory 19.

The adder 17 adds signals output from the IDCT unit 16 and the frame memory 19 to restore the image signal, and stores the same in the frame memory 19 to compensate for the motion of the next frame. In order to change the signal output by the line unit is output to the slice buffer 18.

3 is a block diagram of the HDTV receiver according to the present invention.

As shown in FIG. 1, the HDTV receiver according to the present invention includes a decoder 2, a frame converting unit 3, a multiplexer 4, a decimation unit 13, a mode converting unit 1, and a display processing unit. (11) and a multiplexer selection control unit 12.

The decoder 2 restores the transmitted compressed signal to the HDTV video signal, and converts the frame to 30 Hz when the frame rate of the restored image output from the decoder 2 is not 30 Hz. Convert.

The multiplexer 4 selects the output of the decoder 2 or the converter 3 according to the frame rate of the reconstructed image.

That is, if the frame rate is 30 Hz, the output of the decoder 2 is selected. If the frame rate is 24 Hz or 60 Hz instead of 30 Hz, the frame is selected and output.

The decimation section 13 includes a 2: 1 decimation section 5, a 3: 2 decimation section 6, the multiplexer 4, a 2: 1 decimation section 5, and a 3: 2 decimation section ( The multiplexer 7 selects among the outputs of 6) and decimates to 525 lines depending on the scanning player of the input image format.

That is, if the scan player of the image input from the multiplexer 4 is 525 lines, the output of the multiplexer 4 is selected, and if the scan player of the input image is 1050 lines, the 2: 1 decimator 5 2: The multiplexer 7 selects one decimated signal, and the multiplexer 7 performs a 3: 2 decimation signal from the 3: 2 decimation unit 6 when the scan player of the input image is 787.5 lines. Select from and print.

The mode conversion unit 1 is an NTSC conversion unit I, II, III (8, 9, 21) and the NTSC conversion unit for converting the signal output from the decimation unit 13 to a display mode desired by the viewer, respectively. I, II, III (8, 9, 21) and the output of the decimator 13 is composed of a multiplexer 10 to select and output according to the desired mode to perform NTSC conversion.

That is, the signal output from the decimation unit 13 according to the mode desired by the user, or the output of the NTSC conversion unit, I, II, III (8, 9, 21) for converting according to each mode is selected by the user. You can choose to display on an existing TV.

The display processing unit 11 processes to display a signal output from the NTSC conversion unit 1 on a monitor.

The multiplexer selection controller 12 retrieves the HDTV video format using the transmitted compressed signal to control the frames S1, S2, and S3 for controlling the frame 3 and the multiplexers 4 and 7. Output

That is, according to whether the frame rate of the input HDTV video signal is 24 Hz or 60 Hz, the control signal S0 is output to the frame rate converter 3 so that the frame rate converter 3 can convert the frame rate. do.

Further, according to whether or not the frame rate of the input HDTV video signal is 30 Hz, the control signal S1 for controlling the selection of the multiplexer 4 is outputted, and when the 30 Hz is received, the multiplexer 4 outputs the decoder 2. If it is not 30Hz but 24Hz or 60Hz, the output of the frame rate converter 3 is selected.

Further, according to whether the scan player of the input HDTV video signal is 525 lines, 1050 lines, or 787.5 lines, the control signal S2 for controlling the selection of the multiplexer 7 is output, and if the line is 525 lines, the multiplexer 7 Select the output of the multiplexer 4 and select the output of the 2: 1 decimation section 5 for 1050 lines and the output of the 3: 2 decimation section 6 for 787.5 lines.

2A, 2B, and 3D are state diagrams of the display mode according to the present invention.

The mode converting unit 1 converts the display according to the display modes I, II, III, and IV desired by the user, as shown in FIG. 2 (a) (b) (c) (d). A) (b) (c) (d)

FIG. 2A is a mode (I) in which a 525-line 16: 9 screen, that is, a mode (I) for directly displaying the output of the decimation unit 13 on a monitor, is required when displaying on a wide screen TV. Do.

FIG. 2B is a mode (II) for displaying on a 4: 3 screen of an existing TV. The image of both sides is removed from the output of the decimation unit 13 and converted to 4: 3 screen. In the case of displaying, the NTSC conversion unit I (8) performs the conversion operation.

2 (c) is a mode (III) in which the output of the decimation unit 13 is decimated horizontally and vertically and displayed on a 4: 3 screen of an existing TV without loss of content. The upper and lower regions are displayed as a black region without an image, and the NTSC converter II (9) performs the conversion operation.

FIG. 2D is a mode (IV) in which the vertical 525 lines are maintained in the output of the decimation unit 13 and decimated only horizontally and displayed on a 4: 3 screen. In this case, the image is compressed horizontally. The NTSC conversion section III (21) performs the conversion operation.

4 is a detailed block diagram of the frame converting unit 3 of FIG. 1, and FIG. 5 is a signal waveform diagram of each part of FIG.

As shown in FIG. 4, the frame rate converter 3 outputs the memory 22, 23, 24 and the output of the memory 23, 24 to which an image signal having a frame rate of 60 Hz or 24 Hz is input and stored. And a multiplexer 25 for selecting, a multiplexer 27 for selecting the outputs of the memory 22 and the multiplexer 25, and a memory controller 26 for controlling the memories 22, 23, and 24.

First, an image signal having a frame rate of 60 Hz is written while skipping one frame to the memory 22 under the control of the memory controller 26 and read at a double speed.

In addition, since a video signal having a frame rate of 24 Hz has a conversion ratio of 4: 5 for conversion to 30 Hz, one frame may be repeatedly read every four frames.

First, the input video signal is divided into units of every four frames, and only the first frame is written to the memory 23, and then read at the output speed, and all four frames are written to the memory 24, and the predetermined delay is read and then read from the memory 23. Start reading as soon as it finishes and stop reading from memory 24 when reading from memory 23.

The signals output through the read operation in the memories 23 and 24 are multiplexed by the multiplexer 25 and converted to 30 Hz.

The multiplexer 27 selects the output of the memory 22 or the multiplexer 25 according to the control signal SO output from the multiplexer selection control unit 12.

That is, if the video signal is 24 Hz, the control signal S0 controls the multiplexer 27 to select the output of the multiplexer 25. If the video signal is 60 Hz, the control signal S0 is the multiplexer 27 the memory. Control to select the output of (22).

The memory controller 26 outputs a read and write control signal for controlling read and write operations of the memories 22, 23, and 24.

Signal waveforms showing the detailed operation of the frame rate converter 2 configured as described above are shown in FIG.

FIG. 6 is a detailed configuration diagram of the 2: 1 decimation section 5 of FIG. 1, and FIG. 7 is a signal waveform diagram of each part of the 2: 1 vertical decimation section 28 of FIG. It is a signal waveform diagram of the 2: 1 horizontal decimation part 36 of 6 degrees.

The 2: 1 decimation unit 5 performs 2: 1 decimation in the horizontal direction with the 2: 1 vertical decimation unit 28 which performs 2: 1 decimation in the vertical direction as shown in FIG. It consists of a 2: 1 horizontal decimation section 36 to perform.

The 2: 1 vertical decimation unit 28 connects a plurality of line delay units 29 in series to remove the aliasing, and outputs signals from the multiplexer 4 and the plurality of line delay units. A memory control section having a filter section 30 for filtering each output of the section 29, and controlling to write and read out the filtered signal output from the filter section 30 to the memory 31 by one line while reading at an output speed. It is configured by connecting the 32 to the memory 31.

That is, the memory controller 32 is provided to control the read and write operations of the memory 31.

The signal waveform showing the detailed operation of the 2: 1 vertical decimation unit 28 configured as described above is shown in FIG.

The 2: 1 horizontal decimation unit 36 serially latches a plurality of latches 33 to remove the aliasing from the signal input from the memory 31 of the 2: 1 vertical decimation unit 28. And a filter unit 34 for filtering signals output from the memory 31 of the 2: 1 vertical decimation unit 28 and respective outputs of the plurality of latches 33, and the filter unit 34 Latched by filtering the filtered signal output from the by one pixel to the latch (35).

The signal waveform showing the detailed operation of the 2: 1 horizontal decimation unit 36 configured as described above is shown in FIG.

FIG. 9 is a detailed configuration diagram of the 3: 2 decimation section 6 of FIG. 1, and FIG. 10 is a signal waveform diagram of each part of the 3: 2 vertical decimation section 49 of FIG. It is a signal waveform diagram of each part of the 3: 2 horizontal decimation part 50 of FIG.

The 3: 2 decimation unit 6 performs 3: 2 decimation in the horizontal direction with the 3: 2 vertical decimation unit 49 which performs 3: 2 decimation in the vertical direction as shown in FIG. It consists of a 3: 2 horizontal decimation section 50 to perform.

The 3: 2 vertical decimator 49 uses the output of the line delay unit 37 and the output of the multiplexer 4 as inputs to the adder 38, and divides the output of the adder 38 by half. The input of the multiplexer 40 and the output of the multiplexer 4 and the half divider 39 to the input of the multiplexer 40, and the output of the multiplexer 40 to the input of the memory 41. The memory controller 42 is configured to control the memory 41, divides the line of the input video signal into three line units, outputs the first line as it is, and calculates the average of the second and third lines. To print to the second line.

That is, by dividing the line of the input video signal into three units, the first line is input to the multiplexer 40, the second line is delayed through the line delay unit 37, and the third line to which the delayed second line is input. The average is obtained through the trailing device 38 and the half divider 39 and output to the multiplexer 40.

The sound multiplexer 40 alternately outputs the first line and the line average, that is, the output of the half divider 39.

The memory 41 stores and outputs only a corresponding line among the lines output from the multiplexer 40, and the memory controller 42 controls reading and writing of the memory 41.

The signal waveform showing the detailed operation of the 3: 2 vertical decimation unit 49 configured as described above is shown in FIG.

The 3: 2 horizontal decimation section 50 passes through the latch 43 to delay the pixel output from the memory 41 of the 3: 2 vertical decimation section 49, and from the latch 43 In order to find the average between the output delayed pixel and the input pixel, the adder 44 and the 1/2 divider 45 are passed through, and the average between the pixels output from the 1/2 divider 45 and the input pixel are The input to the multiplexer 46 is selected to be output to the 1: 3 demultiplexer 47, and the output of the 1: 3 demultiplexer 47 is again output through the 2: 1 multiplexer 48.

That is, the multiplexer 46 multiplexes the average of the input pixels in the multiplexer 46 and discards one phase out of three phases through the 1: 3 demultiplexer 47 and selects only two phases (P-hase). One is input to multiplexer 48 and multiplexed to obtain the desired output.

Signal waveforms showing the detailed operation of the 3: 2 horizontal decimation unit 50 configured as described above are shown in FIG.

FIG. 12 is a detailed configuration diagram of the NTSC conversion section I (8) of FIG.

As shown in FIG. 12, the NTSC converter I (8) includes a memory 51 for storing signals output from the multiplexer 7 in line units and a memory controller 52 for controlling the memory 51. 2 is converted to the mode (II) to display on the 4: 3 screen of the existing TV as shown in FIG.

That is, the memory controller 21 reads and outputs only necessary pixels after storing one line of the output of the multiplexer 7 in the line memory 51 in order to cut an area existing on both sides of the frame in the horizontal direction. Adjust the write address.

FIG. 13 is a detailed configuration diagram of the NTSC converter II 9 of FIG. 1, and FIG. 14 is a signal waveform diagram of each part of FIG.

As shown in FIG. 13, the NTSC conversion unit II 9 includes a K: L horizontal decimation unit 53 and a frame memory 56 which are composed of a 1: k demultiplexer 54 and an L: 1 multiplexer 55. As shown in FIG. And a memory control unit 57, and decimates horizontally and vertically as shown in FIG. 2 (c) to display the content on a 4: 3 screen without loss of content and to display the upper and lower portions of the screen as a black area.

That is, when the ratio of decimation to be displayed on a 4: 3 screen is K: L, the output of the multiplexer 7 is demultiplexed in the 1: K demultiplexer 54, and the 1: K demultiplexer 54 is demultiplexed. Only the desired L phase of the demultiplexed signal is multiplexed by the L: 1 multiplexer 55 to decimate in K: L.

The signal to be output from the K: L horizontal decimation unit 53 is stored in the frame memory 56, vertical decimation under the control of the memory controller 57, and the portion to be displayed, which is not stored, That is, the upper and lower portions of the screen are both set to '0' and written in the area to be displayed. In this case, the lines to be decimated may be implemented by adjusting the write enable signal.

The memory controller 57 generates a write enable signal to control the frame memory 56 to perform decimation. In FIG. 14, the memory controller 57 controls the frame memory 56 to vertically decimate at a 3: 2 ratio. In one embodiment, a write enable signal that is operated by a second embodiment is shown.

FIG. 15 is a detailed block diagram of the NTSC converter II 12 of FIG.

The NTSC conversion unit III (12) is composed of a 1: K demultiplexer 58 and an L: 1 multiplexer 59 as shown in FIG. 15, and is desiccated in the horizontal direction as shown in FIG. To convert to mode (IV).

When the decimation ratio is K: L, the demultiplexer 58 demultiplexes 1: K, and only the desired L phase (Phase) of the signals output from the 1: K demultiplexer 58 is received in the L: 1 multiplexer 59. Multiplex and decimate with K: L.

According to the present invention configured and operated as described above, when the transmitted video format is one of a plurality of formats, the present invention can be displayed on a conventional TV in various modes, so that an HDTV broadcast can be viewed on a conventional TV.

Claims (18)

Decoding means (2) for restoring an ADTV (HDTV) video signal input to any one of a plurality of video formats; Control means for outputting a control signal in accordance with the frame rate of the input video format and the scanning player; Frame rate converting means (3) for converting the frame rate of the signal output from the decoding means into a frame rate of NTSC standard in accordance with the control signal; And a plurality of decimation units for converting the frame-scanning signal output from the converting means into an NTSC-type scanning player according to the type of HDTV video format. Decimation means (13) for decimating according to a control signal; Mode conversion means (1) for converting the signal output from the decimation means into a desired display mode; And a display processing means (1) for processing a signal output from the mode converting means to be displayed on a monitor. 2. The apparatus according to claim 1, wherein said decoding means (2) comprises a variable length decoder (VLD) and demultiplexing means (14) for decoding an input compressed bitstream into a meaningful signal, and said VLD and demultiplexing means ( Inverse quantization means 15 for inverse quantization of the signal outputted from 14), IDCT means 16 for inverse discrete costine transform (IDCT) processing of the signal output from the inverse quantization means 15, and the VLD and demultiplexing means. Motion compensation means 20 for motion compensation using signals output from 14, frame memory means 19 for storing signals output from the motion compensation means 20, the IDCT means 16 and the frame Adder 17 for adding the signal output from the memory means 19 to the frame memory means 19 and a slice for converting the signal output from the adder 17 in units of lines. HDTV receiver, characterized in that the buffer means (18). 2. The decimation means (3) according to claim 1, wherein the decimation means (13) decimates a signal output from the first multiplex means (4) by 2: 1 decimation means (5) and the first multiplexing means (4). The first multiplexing means 4 and the 2: 1 decimating means (3) under the control of the 3: 2 decimation means 6 and the multiplexer selection control means 12 for decimating a signal output from 5) and a second multiplexing means (7) for selecting and outputting the output of the 3: 2 decimation means (6). The display mode of claim 1, wherein the display mode is a mode (I) for displaying on a 16: 9 screen, a mode (II) for removing the images on both sides of the screen, and displaying the screen on a 4: 3 screen. HDTV which is composed of mode (III) which displays on 4: 3 screen without loss of contents and the upper and lower areas are processed as black area and mode (IV) which decimates horizontally and displays on 4: 3 screen. Receiver. 5. The method according to claim 4, wherein the mode converting means 1 converts the signals output from the decimation means 13 into respective modes II, III, IV according to a desired display mode. Display modes (I, II) for which signals output from the third NTSC converter (8, 9, 12) and the first, second and third NTSC converters (8, 9, 12) and the decimation means (13) are desired. , III, IV) DHTV receiver characterized in that it comprises a second multiplexing means (10) for selecting and outputting. 2. The multiplexer selection control means (12) according to claim 1, wherein the multiplexer selection control means (12) controls the operation of the frame rate converting means (3) according to whether the frame rate of the input signal is 24 Hz or 60 Hz, and the frame rate of the input signal. HDTV receiver, characterized in that the control of the selection of the first multiplexing means (4) in accordance with whether or not 30Hz, and the operation of the decimation means (7) in accordance with the scanning player of the input signal. 4. The signal of claim 3, wherein the 2: 1 decimation means (5) receives a signal output from the 2: 1 vertical decimation means (28) and the vertical decimation means (28) for 2: 1 decimation in the vertical direction. And a 2: 1 horizontal decimation means (36) for 2: 1 decimation in the horizontal direction. The method of claim 3, wherein the 3: 2 decimation means (6) is output from the 3: 2 vertical decimation means (49) and the 3: 2 vertical decimation means (49) for 3: 2 decimation in the vertical direction. An HDTV receiver, comprising: 3: 2 horizontal decimation means (50) for decimating a signal to be 2: 2 in the horizontal direction. 6. The pixel according to claim 5, wherein the second mode converting means (8) controls the memory means (51) for storing signals output from the decimation means (13) and the memory means (51). HDTV receiver, characterized in that consisting of memory control means 52 to read only. 6. The second mode converting means (9) according to claim 5, wherein the second mode converting means (9) outputs from the horizontal decimation means (53) and the horizontal decimation means (53) for horizontally decimating the signal output from the decimation (13). Frame memory means 56 for storing the signal to be stored and memory control means 57 for controlling the frame memory means 56 to decimate vertically and to set the portion displayed as the black area to '0'. HDTV receiver, characterized in that. 6. The third mode converting means (12) according to claim 5, characterized in that the third mode converting means (12) comprises demultiplexing means (58) and third multiplexing means (59) for horizontally decimating the signal output from the decimation means (13). HDTV receiver, characterized in that. 8. The method of claim 7, wherein said 2: 1 vertical decimation means (28) comprises a plurality of line delay means (29) connected in series for delaying a signal output from said first multiplexing means (4) and said first multiplexing means. (4) and filter means (30) for filtering signals output from the plurality of line delay means (29), memory means (31) for storing signals from the filter means (30), and the memory means (31). HDTV receiver, characterized in that consisting of a memory control means 32 to control by skipping line by line. The method of claim 7, wherein the 2: 1 horizontal decimation means (36) comprises a plurality of latch means (33) connected in series to delay the signal output from the 2: 1 vertical decimation means (28). 1 a filtering means 34 for filtering signals output from the vertical dimming means 28 and the plurality of latch means 33 and a latch means for latching while skipping the signals output from the filter means 34 by one pixel ( HDTV receiver, characterized in that consisting of 35). The method according to claim 8, wherein the 3: 2 vertical decimation means (49) comprises line delay means (37) for delaying a signal output from the first multiplexing means (4), and the first multiplexing means (4). An average output from the adder 38 and the divider 39, the signal output from the first multiplexing means 4, and the divider 39, which calculate the average of the signal output from the line delay means 37. A third multiplexing means 40 for selecting and outputting a signal, a memory means 41 for storing a signal output from the third multiplexing means 40, and a memory control means 42 for controlling the memory means 41. HDTV receiver, characterized in that configured. The method of claim 8, wherein the 3: 2 horizontal decimation (50) is latch means 43 for delaying the signal output from the 3: 2 vertical decimation means 49 in units of pixels, the latch means 43 Calculate the average of the signal output from the 3: 2 vertical decimation means 49 and the output signal from the 3: 2 vertical decimation means 49 A third multiplexing means 46 for selecting and outputting a signal and an average signal output from the dividing means 45, and a 1: 3 demultiplexing means for 1: 3 demultiplexing a signal output from the third multiplexing means 46 ( 47) and 2: 1 multiplexing means (48) for 2: 1 multiplexing by selecting from signals output from said 1: 3 demultiplexing means (47). 12. The signal of claim 10, wherein the horizontal decimation means (53) is a demultiplexing means (54) for demultiplexing the signal output from the decimation means (13) and a signal output from the demultiplexing means (54). HDTV receiver, characterized in that consisting of the third multiplexing means (55) for selecting and multiplexing only. 2. The frame rate converting means (3) according to claim 1, characterized in that the frame rate converting means (3) comprises: first memory means (22) for converting an input signal into a video signal having a frame rate of 30 Hz when the frame rate is 60 Hz, In case of 24Hz, signals output from the second and third memory means 23 and 24 and the second and third memory means 23 and 24 for storing the video signal are converted to a video signal having a frame rate of 30 Hz. Third multiplexing for selecting and outputting signals output from the second multiplexing means 25 for multiplexing, the first memory means 22 and the second multiplexing means 25 under the control of the multiplexer selection control means 12. HDTV receiver, characterized in that consisting of means (27). Decoding means for restoring an HDTV (HDTV) video signal input to any one of a plurality of video formats; Control means for outputting a control signal in accordance with the frame rate of the input video format and the scanning player; Frame rate converting means for converting a frame rate of the signal output from the decoding means into a frame rate of NTSC standard according to the control signal; A plurality of decimation units for converting a scan player of the signal output from the frame rate converting unit into a scan player of NTSC standard are provided in accordance with the type of HDTV video format. HDTV receiver comprising a decimation means for decimating according to a control signal.