KR950016348A

KR950016348A - HDTV receiver

Info

Publication number: KR950016348A
Application number: KR1019930024121A
Authority: KR
Inventors: 이동호
Original assignee: 이헌조; 엘지전자 주식회사
Priority date: 1993-11-13
Filing date: 1993-11-13
Publication date: 1995-06-17
Also published as: KR960013648B1

Abstract

본 발명은 HDTV 수신장치에 관한 것으로, 입력되는 압축된 비트스트림을 HDTV 영상신호로 복원하는 디코딩 수단(2), 상기 디코딩수단(2)으로 부터 출력되는 신호의 프레임율을 변환하는 프레임율 변환수단(3), 상기 디코딩 수단(2)과 프레임율 변환수단(3)으로 부터 출력되는 신호를 프레임율에 따라 선택하여 출력하는 제1멀티플렉싱수단(4), 상기 제1멀티플렉싱수단(4)으로 부터 출력되는 신호의 주사선수가 525라인이 되도록 데시메이션하는 데시메이션수단(13), 상기 데시메이션수단(13)으로 부터 출력되는 신호를 원하는 디스플레이 모드로 변환하는 NTSC 변환수단(1), 상기 NTSC 변환수단(1)으로 부터 출력되는 신호를 모니터에 디스플레이 할수 있도록 처리하는 디스플레이 처리수단(11) 및 상기 압축된 비트스트림으로 부터 검출된 영상 포맷에 따라 상기 프레임율 변환수단(3), 제1멀티플렉싱수단(4) 및 데시메이션수단(13)을 제어하는 멀티플렉서 선택제어수단(12)을 포함하여 구성되는 것을 특징으로 한다. 따라서 본 발명은 여러가지 모드로 기존의 TV에 디스플레이 할 수 있는 효과가 있다.The present invention relates to an HDTV receiver, comprising: decoding means (2) for reconstructing an input compressed bitstream into an HDTV video signal, and frame rate conversion means for converting a frame rate of a signal output from the decoding means (2). (3) from the first multiplexing means (4) and the first multiplexing means (4) for selecting and outputting signals output from the decoding means (2) and the frame rate converting means (3) according to the frame rate Decimation means 13 for decimating the output signal of the output signal to be 525 lines, NTSC conversion means 1 for converting the signal output from the decimation means 13 to a desired display mode, and the NTSC conversion Display processing means (11) for processing a signal output from the means (1) to be displayed on a monitor and the frame according to the image format detected from the compressed bitstream. And a rate converting means (3), first multiplexing means (4) and characterized in that the decimator comprises a decimation means 13, multiplexer select control means 12 for controlling the. Therefore, the present invention has the effect that can be displayed on the existing TV in various modes.

Description

HDTV receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 HDTV 수신장치의 구성도,1 is a block diagram of an HDTV receiver according to the present invention;

제2도는 (가)(나)(다)(라)는 본 발명에 의한 디스플레이 모드의 상태도,2 is (a) (b) (d) (d) is a state diagram of a display mode according to the present invention;

제3도는 제1도의 디코더의 새부구성도,3 is a new configuration diagram of the decoder of FIG.

제4도는 제1도의 프레임 변환부의 세부구성도,4 is a detailed configuration diagram of the frame converter of FIG.

제5도는 제4도의 각 부분의 신호파형도,5 is a signal waveform diagram of each part of FIG.

제6도는 제1도의 2 : 1 데시메이션부의 세부구성도.6 is a detailed configuration diagram of the 2: 1 decimation part of FIG.

Claims

Decoding means (2) for reconstructing the compressed bitstream input to the HDTV video signal, frame rate converting means (3) for converting the frame rate of the signal output from said decoding means (2), and said decoding means (2) And the first multiplexing means 4 for selecting and outputting a signal output from the frame rate converting means 3 according to the frame rate, and 525 lines of scan signals of the signal output from the first multiplexing means 4. Display the decimation means 13, the NTSC conversion means 1 for converting the signal output from the decimation means 13 into a desired display mode, and the signal output from the NTSC conversion means 1 on the monitor. The frame rate converting means (3), the first multiplexing means (4), and the decimation means according to the display processing means (11) and the image format detected from the compressed bitstream. And a multiplexer selection control means (12) for controlling (13).

2. The apparatus according to claim 1, wherein said decoding means (2) comprises a variable length decoder (VLD) and demultiplexing means (14), and said VLD and demultiplexing means (14) for decoding an input compressed bitstream into a meaningful signal. Inverse quantization means 15 for inverse quantization of the signal outputted from the IDCT means 16 for processing an Inverse Discrete Cosine Transform (IDCT) output from the inverse quantization means 15, the VLD and demultiplexing means ( 14, a motion compensation means 20 for compensating for motion using the signal output from 14, a frame memory means 19 for storing a signal output from the motion compensating means 20, and the IDCT means 16; In order to convert the signal output from the frame memory means 19 by the addition means 17 for outputting the frame memory means 19 and the signal output from the adding means 17 in line units. HDTV receiving device being configured to slice buffer means (18).

2. The apparatus according to claim 1, wherein the frame converting section (3) comprises: first memory means (22) for converting the input signal into a video signal having a frame rate of 30 Hz when the frame rate is 609 Hz, At 24 Hz, signals output from the second and third memory means (23, 24) and the second and third memory means (23, 24) for storing the video signal for conversion to a video signal having a frame rate of 30 Hz. A second multiplexing means (25) for multiplexing the signals output from the first memory means (22) and the second multiplexing means (25) and selecting and outputting the signals under the control of the multiplexer selection control means (12). HDTV receiver, characterized in that consisting of three multiplexing means (27).

2. The decimation means (3) according to claim 1, wherein the decimation means (13) decimates a signal output from the first multiplexing means (2) by 2: 1 decimation means (5) and the first multiplexing means (4). The first multiplexing means 4 and the 2: 1 decimation means under the control of the 3: 2 decimation means 6 and the multiplexer selection control means 12 for decimating the signal output from And (5) and second multiplexing means (7) for selecting and outputting the output of the 3: 2 decimation means (6).

The display mode of claim 1, wherein the display mode is a mode (I) for displaying on a 16: 9 screen, a mode (II) for removing the images on both sides of the screen and displaying the image on a 4: 3 screen, and decimating vertically and horizontally. HDTV which is composed of mode (III) which displays on the lower surface of 4: 3 without loss of content, and processes the upper and lower areas as black area (III) and horizontally decimates to display on 4: 3 screen (IV). Receiver.

6. The first and second NTSC converting means (1) according to claim 5, wherein the NTSC converting means (1) converts a signal output from the decimating means (13) into respective modes (II, III, IV) according to a desired display mode. And a display mode in which a signal output from the third NTSC converter 8, 9 and 12, the first, second and third NTSC converters 8, 9 and 12 and the decimation means 13 is output. And a second multiplexing means (10) for selecting and outputting according to I, II, III, IV).

2. The multiplexer selection control means (12) according to claim 1, wherein the multiplexer selection control means (12) controls the operation of the frame rate converting means (3) according to whether the frame rate of the input signal is 24 Hz or 60 Hz, and the frame rate of the input signal. HDTV receiver, characterized in that the control of the selection of the first multiplexing means (4) in accordance with whether or not 30Hz, and the operation of the decimation means (7) in accordance with the scanning player of the input signal.

5. The signal output from the vertical decimation means (28) according to claim 4, wherein the 2: 1 decimation means (5) is output from the 2: 1 vertical decimation means (28) and the vertical decimation means (28) for decimating 2: 1 in the vertical direction. And a 2: 1 horizontal decimation means (36) for 2: 1 decimation in the horizontal direction.

5. The method according to claim 4, wherein the 3: 2 decimation means (5) is from the 2: 2 vertical decimation means (49) and 2: 3 vertical decimation means (49) for 2: 2 decimation in the vertical direction. An HDTV receiver comprising: a 3: 2 horizontal decimation means (50) for decimating an output signal in a horizontal direction.

7. The pixel arrangement according to claim 6, wherein the first NTSC conversion means (8) controls the memory means (51) for storing the signal output from the decimation means (13) and the memory means (51). HDTV receiver, characterized in that consisting of memory control means 52 to read only.

The horizontal decimation means (53) and the horizontal decimation means (53) according to claim 6, wherein said second NTSC converting means (9) horizontally decimates a signal output from said decimation means (13). Memory control means for controlling the frame memory means 56 and the frame memory means 56 for storing the signal output from the (6) to decimate vertically and set the portion dispelled to the black region to '0' ( 57) HDTV receiver characterized in that consisting of.

7. The third NTSC converting means (12) according to claim 6, wherein said third NTSC converting means (12) comprises demultiplexing means (58) and third multiplexing means (59) for horizontally decimating a signal output from said decimation means (13). HDTV receiver, characterized in that.

9. The method of claim 8, wherein the 2: 1 vertical decimation means (28) comprises a plurality of line delay means (29) serially connected to delay the signal output from the first multiplexing means (4), the first multiplexing. Filter means 30 for filtering signals output from the means 4 and the plurality of line delay means 29, memory means 31 for storing signals output from the filter means 30 and the memory. HDTV receiver characterized in that it comprises a memory control means (32) to control the means (31) so as to skip and save line by line.

9. The method according to claim 8, wherein the 2: 1 horizontal decimation means (36) comprises a plurality of latch means (33) connected in series to delay the signal output from the 2: 1 vertical decimation means (28). : 1 latching while filtering the signal output from the vertical decimation means 28 and the plurality of latch means 33 and the signal output from the filter means 34 by one pixel. HDTV receiver, characterized in that consisting of latch means (35).

10. The method according to claim 9, wherein the 3: 1 vertical decimation means (49) comprises a line delay means (37) for delaying a signal output from the first multiplexing means (4), and the first multiplexing means (4). An output from the adder 38 and the divider 39, which calculates the average of the signal output from the line delay means 37, and the signal and divider 39, output from the first multiplexing means 4; A third multiplexing means 40 for selecting and outputting an average signal to be output, a memory means 41 for storing a signal output from the third multiplexing means 40, and a memory control means for controlling the memory means 41; HDTV receiver, characterized in that consisting of (42).

The method of claim 9, wherein the 3: 2 horizontal decimation means (50) comprises: latch means (43) for delaying the signal output from the 3: 2 vertical decimation means (49) on a pixel basis; 43 calculates an average of the signal output from the 3: 2 vertical decimation means 49 and the addition means 44 and the division means 45, and the 3: 2 vertical decimation means 49 The third and second multiplexing means 46 for selecting and outputting the signal output from the signal and the average signal output from the dividing means 45 and the signal output from the third multiplexing means 46. HDTV comprising: a 1: 3 demultiplexing means 47 for multiplexing and a 2: 1 multiplexing means 48 for 2: 1 multiplexing by selecting from signals output from the 1: 3 demultiplexing means 47 Receiver.

12. The apparatus according to claim 11, wherein the horizontal decimation means (53) outputs from the demultiplexing means (54) and the demultiplexing means (54) for demultiplexing the signal output from the decimation means (13). And a third multiplexing means (55) for selecting and multiplexing only a desired signal among the signals.

※ Note: The disclosure is based on the initial application.