KR100255773B1 - Cosine transmitter of digital tv receiver decoder - Google Patents

Abstract

PURPOSE: An inverse discrete cosine converter of a digital TV receiving decoder is provided to improve the image quality by providing an integration IDCT which considers a luminescence and a chrominance signal and performs a sampling according to different sizes. CONSTITUTION: ROMs(801-804) perform an integration IDCT of bit streams(800). 4 multipliers(805-808) multiply IDCT conversion coefficient information provided from the ROMs(801-804) by the bit streams inputted. Adders(809-816) perform an addition or a subtraction according to results multiplied are inputted. Registers(817-824) stores the results added or subtracted. A signal(825) controls an addition or a subtraction operation of the adders(809-816). The first multiplexer(826) selects an 8 point IDCT value(827) in an SDTV mode. The second multiplexer(828) selects a 4 point IDCT value(829) in an HDTV mode.

Description

Inverse Discrete Cosine Converter of Digital TV Receive Decoder Device

The present invention compresses and transmits an image signal, and inverse discrete cosine transform (IDCT) in an image decoder device of a digital TV receiver for decoding and displaying the transmitted compressed image signal in a decoder of a receiver. )

As an embodiment, the present invention provides a digital TV decoder that receives an MPEG video signal and decodes the received video signal, wherein the downsampling size is different in a decoder device for receiving an HD video using an SDTV receiver. The present invention relates to an inverse discrete cosine converter of a digital TV receiver decoder device capable of integrating two systems of IDCT.

The digital TV receiver decodes the video signal compressed and transmitted in MPEG2 by the decoder and displays it on the screen.

Typically, digital TV receivers are roughly classified into HDTV class and SDTV class according to the number of pixels (pel = picture elements) taking into consideration factors affecting sharpness / image reproduction performance (quality). It has a performance of up to 1920pels / 1080lines and SDTV, for example, 640pels / 480lines.

Fig. 1 shows an example of a decoder in a digital TV receiver, one pixel is represented by 8 bits, one macro block has a data structure of 16 * 16 pixels, and corresponds to each class including motion vector information. Handles a bitstream of the level.

In Figure 1, Variable Length Decoder (VLD) 1 variable length decodes the input bit stream data, IDCT 2 decodes the variable length decoded data by Inverse Discrete Cosine Transform, The adder 3 stores the reconstructed image in the frame memory 5 by using the motion compensated information of the motion estimation compensator 4 in the decoded data, and the reconstructed original image signal is output to the display means ( Video out)

FIG. 2A illustrates a 2D 8 * 8 IDCT process, in which the IDCT 202 is performed in the horizontal direction with respect to the 8 * 8DCT block 201 and the IDCT 203 is performed in the vertical direction to perform the image block 204. Getting

Since the HDTV receiver receives and decodes HD class data, there is no obstacle in receiving and decoding SD data.

Since the SDTV receiver receives and decodes the SD level data, there is no obstacle in receiving and decoding the SD level data, but from the viewpoint of compatibility, the SDTV receiver should be able to receive and process (decode / display) the HD level data.

To this end, the decoder of the SD TV receiver performs 'data processing' for the SD reception of HD data.

This data processing process is secured through downsampling-filtering / decimation.

Figure 2b shows a simple example of a downsampling method of a decoder device for receiving, decoding and displaying HD data in an SD TV receiver.

The method subsamples 206 the image block 205 in the horizontal direction, halving in the horizontal direction, and subsampling 208 in the vertical direction again with respect to the image block 207 which is this horizontal ½ line. By reducing the half-sample in the vertical direction to obtain the downsampled image block 209.

Conventionally, in a decoder device for receiving HD-quality video from an SDTV receiver, IDCT for down-sampled HDTV video reception (decoding) and IDCT for normal (SDTV) video reception (decoding) are separately provided, and two decoding are performed. It should have a separate ROM with each IDCT coefficient information corresponding to each mode.

The present invention provides an integrated IDCT in a digital TV receiver decoder which downsamples to different sizes in consideration of both color signals and luminance signals together with I, P, and B pictures as a factor that affects the quality of a reproduced image.

The present invention provides an integrated IDCT, wherein even when a decoder processes both an HD class bit stream and an SD class bit stream, all operations are performed in one integrated IDCT without having a plurality of IDCTs.

In particular, the present invention provides an integrated IDCT that performs operations through one IDCT and handles filtering and decimation operations (downsampling) together even when the SDTV receiver outputs outputs having different points through downsampling. to provide.

In the present invention, integrated IDCT is implemented by storing a plurality of coefficient values in a ROM using symmetry of IDCT operation and selectively using them according to characteristics of an input image.

1 is a block diagram of a digital TV receiver decoder

Figure 2a shows a 2D 8 * 8 IDCT process

2b illustrates a subsampling process of a 2D image.

3 is a block diagram of a decoder device to which the present invention is applied.

4 illustrates an IDCT / decoding process of progressive data.

5 is a diagram illustrating an IDCT / decoding process of interlaced data.

Figure 6 is a block diagram showing a conventional IDCT concept

7 is a block diagram showing the IDCT concept of the present invention

8 is a block diagram of an IDCT of the present invention

3 is an embodiment of a digital TV receiver decoder device to which the integrated IDCT of the present invention is applied, and downsamples luminance signals I and P pictures to 8 * 4, and downsamples luminance signals B pictures and color signals to 4 * 4. Example.

Hereinafter, the present invention will be described by way of examples.

First, let's look at the configuration

First IDCT / downsampling means 31 for performing IDCT and 8 * 4 downsampling in the horizontal direction with respect to IY and PY 32 by inputting the DCT coefficient 30, and the 8 * 4 data and motion compensation. A first adding means 33 for adding and outputting information, a first encoder 34 for performing 8 * 4 data bit reduction encoding output from the first adding means 33, and the first encoder output. A first frame memory (35) for storing the data, a first decoder (36) for decoding the output of the first frame memory (35), and an output of the first decoder (36) for motion vector information (40). 1) Upsampling means 37 for horizontally upsampling and outputting 8 * 8 data, and the output of the first upsampling means 37 in consideration of the motion vector information 40. The first motion compensator 38 and the output of the first motion compensator 38 are downsampled to 8 * 4 for the addition. First downsampling means (39) for inputting to the apparatus 33 as motion compensation processing information;

A second IDCT / downsampling means 41 for performing IDCT and 4 * 4 downsampling in the vertical / horizontal direction with respect to the BY, IC, PC, BC 42 by inputting the DCT coefficient 30; A second adding means 43 for adding and outputting * 4 data and motion compensation information, and a second encoder 44 for performing bit reduction encoding of 4 * 4 data output from the second adding means 43; A second frame memory 45 for storing the second encoder output, a second decoder 46 for decoding the output of the second frame memory 45, and an output of the second decoder 46; Second upsampling means 47 for upsampling horizontally and vertically in consideration of the motion vector information 40 and outputting the data as 8 * 8 data, and outputting the output of the second upsampling means 47 to the motion vector information ( Considering 40), the second motion compensator 48 performs the motion compensation prediction process and the output of the second motion compensator 48 is 4 * 4 horizontally / vertically. Operating sampled by the second down sampling means (49) for inputting a motion compensation processing information to said adder (43) and;

Third downsampling means 50 for vertical downsampling the 8 * 4 output of the first decoder 36 to 4 * 4, the output of the second downsampling means 50 and the second decoder ( A multiplexer 51 for outputting the output of 46 as a final decoded video signal;

It is configured to include.

The first IDCT / downsampling means 31 performs inverse discrete cosine conversion of the input DCT coefficient 30 and performs downsampling in the horizontal direction to reduce the size of 8 * 8 to 8 * 4.

Here, downsampling is performed on the luminance I picture IY and the luminance P picture PY and inputs this 8 * 4 data to the first adder 33.

IDCT / downsampling to M * N (8 * 4) is presented in various ways and will be described later.

The result of performing 8 * 4 horizontal downsampling on the 8 * 8 IY, PY macroblocks as described above is applied to the first adder 33.

The output of the first adder 33 is input to the first encoder 34 performing bit reduction encoding to reduce the amount of bits by using the correlation of adjacent pixels in consideration of the capacity limitation of the first frame memory 35.

The bit amount is reduced to 14 bits by removing 2 samples in consideration of the correlation of adjacent pixels in the horizontal (or vertical) direction based on 8 * 4.

An example of a method of reducing the number of bits is DPCM.

The downsampling data is encoded with horizontal (or vertical) pixels x1, x2 with values of x1 and x2-x1, where x1 is encoded as an 8-bit value, x2-x1 is encoded as a 6-bit value, or x1 is As an 8-bit value, x2-x1 encodes a 6-bit non-uniformly quantized value.

This process is similarly performed for the second encoder 44.

The bit-reduced data by the DPCM technique as described above is stored in the first frame memory 35 and decoded by the first decoder 36 through an inverse process of the decoding for image restoration (reproduction).

The decoded 8 * 4 data is upsampled in the horizontal direction by the first sampling means 37 which receives the motion vector information 40 for motion compensation and output as 8 * 8 data.

The upsampled 8 * 8 data is input to the first motion compensator 38 and motion compensated by the motion vector information 40, and the motion compensated information is 8 * 8 in size to the first downsampling means 39. Is entered.

The first downsampling means 39 horizontally downsamples the input 8 * 8 motion compensation information into 8 * 4 and supplies it to the first adder 33, whereby the first IDCT / downsampling means 31 makes the 8 * 8 motion compensation information. A motion compensated I, P picture luminance signal corresponding to IY and PY data (size) downsampled to 4 is outputted.

By repeating the above process, IY and PY data processing is performed, and 8 * 4 data bit-decoded from the first frame memory 35 is vertically downsampled to 4 * 4 size while passing through the third downsampling means 50. And matched to multiplexer 51 (to match BY, IC, PC, BC downsampled to 4 * 4).

The second IDCT / downsampling means 41 performs inverse discrete cosine conversion of the input DCT coefficient 40 and downsamples the horizontal / vertical direction to reduce the size of 8 * 8 to 4 * 4.

Here, downsampling is performed on the luminance B picture BY and the color signals IC, PC, BC and inputs this 4 * 4 data to the second adder 43.

IDCT downsampling with K * L (4 * 4) will also be described later.

As a result of performing the 4 * 4 horizontal and vertical downsampling on the 8 * 8 BY, IC, PC, BC macroblocks, the second adder 43 is applied.

The output of the second adder 43 is input to the second encoder 44 which performs bit reduction encoding by the DPCM technique, and takes into account the bit amount by using the correlation of adjacent pixels in consideration of the capacity limitation of the second frame memory 45. Reduce

The bit-reduced data by the DPCM technique as described above is stored in the second frame memory 45, and decoded by the second decoder 46 through the reverse process of the decoding for image restoration (reproduction).

The decoded 4 * 4 data is upsampled in the horizontal / vertical direction by the second sampling means 47 which receives the motion vector information 40 for motion compensation, and is output as 8 * 8 data.

The upsampled 8 * 8 data is input to the second motion compensator 48 and motion compensated by the motion vector information 40, and the motion compensated information is 8 * 8 in size to the second downsampling means 49. Is entered.

The second downsampling means 49 supplies the second adder 43 by horizontally / vertically downsampling the input 8 * 8 motion compensation information 4 * 4 to the second adder 43, whereby the second IDCT / downsampling means 41 Outputs motion compensated BY, IC, PC, and BC data down to 4 * 4 downsampled data (size).

By repeating the above process, BY, IC, PC, BC data processing is performed, 4 * 4 data bit-decoded from the second frame memory 45 is input to the multiplexer 51, the third downsampling means ( Reconstructed together with the IY and PY data outputted at 50), the video is finally output as a down sampled 4 * 4 video signal (video out).

As such, when a high-definition image is received and processed by an SDTV receiver using MPEG2, it is possible to downsample a picture of high importance that affects the image quality of the reproduced image to include more information than the picture that is not. I can reproduce it.

FIG. 4 is a diagram for explaining decoding of a video signal source in a progressive scanning method, and illustrates a concept of 1D-IDCT / downsampling.

Horizontal image 1D-IDCT / filtering and decimation are performed on the image data of one block unit 401 to obtain IDCT and downsampled image block 403, and the vertical 1D-IDCT ( 404 is performed to obtain an IDCT image block 405.

Further, IDD and downsampled image blocks 407 are obtained by performing vertical 1D-IDCT / filtering and decimation 406 on the horizontal 1D-IDCT and downsampled image blocks 403.

FIG. 5 is a diagram for explaining interlaced source decoding of a parallel scan method having a top field and a bottom field, and illustrates the concept of 1D-IDCT / downsampling. The black and white dots distinguished the pixels of the top field and the bottom field).

1D-IDCT / filtering and decimation 502 in the horizontal direction is performed on the image data of one block unit 501 having a top field and a bottom field, and an image block having IDCT and downsampled top field and bottom field ( 503, and 1D-IDCT 504 in the vertical direction is performed to obtain image blocks 505 of IDCT topfield and bottomfield.

In addition, vertical 1D-IDCT / filtering and decimation 506 are performed on the horizontal 1D-IDCT and downsampled topfield and bottomfield image blocks 503 to perform IDCT and downsampled topfield and bottomsampled image. The image block 507 of the field is obtained.

6 is an IDCT circuit in a conventional HDTV / SDTV shared decoder.

As described above, the SD TV receiver has an SDTV mode for decoding an SD image and an HDTV mode for decoding (downsampling) an HD image.

Therefore, in HDTV mode, filtering and decimation is performed along with IDCT to reduce the size of HD-quality video so that it can be displayed on an SD-TV receiver.

That is, it implements 1D-IDCT (602) that receives 8 DCT coefficients and outputs 8 pels, and 1D-IDCT / filtering and decimation (604) that receives 8 DCT coefficients and outputs 4 pels, respectively. Coefficient information for each is received from each of the ROMs 601 and 602. (The IDCT coefficient value is given to receive an appropriate IDCT coefficient according to each mode).

The horizontal and vertical directions, that is, 2D-IDCT and downsampling are the same as described with reference to FIGS. 2A and 2B.

Fig. 7 is a block diagram showing the concept of the integrated IDCT of the present invention, in which an arithmetic circuit 702 using four multipliers corresponds to the IDCT coefficients corresponding to the SDTV mode and the HDTV mode (also known in advance). And 8 IDCT coefficients of HDTV or SDTV with reference to the value of the ROM 701 having the " recorded " In the case of decoding, the image data IDCTed to 8 pixels is output.

For this purpose, an HD / SD selection control signal, a picture selection signal, a field / frame selection signal are input, an address signal of a ROM is output, and an addition or subtraction selection signal (+/-) for calculation is provided. do.

8 shows an inverse discrete cosine converter of the digital TV receiver decoder device of the present invention.

ROMs 801-804 for performing integrated IDCT on the input HDTV or SDTV-class bitstream 800, and four multiplication operators 805- multiplying the IDCT conversion coefficient information provided from the ROM to the input bitstream. 808).

A subtractor (809-816) for adding or subtracting the multiplied value, a register (817-824) for storing the subtraction or addition result, and a signal (825) for controlling the subtraction or addition operation of the subtractor )

It also has a first multiplexer 826, which selects an 8-point IDCT value 827 in SDTV mode, and has a second multiplexer 828, which has 4 points in HDTV mode. IDCT value 829 is selected (filtering and decimation).

8 is a 1D-IDCT / downsampler circuit, and by cascading this in two stages, a 2D-IDCT / downsampler is implemented.

The integrated IDCT circuit configured in this way performs IDCT / downsampling for three cases.

That is, in FIG. 3, 8 * 8 IDCT is performed for 8 * 8 blocks in case of normal reception (SDTV level video reception), and 8 * for 8 * 8 blocks of IY and PY for HDTV level video reception. 4 IDCT / downsampling (filtering / decimation) is performed, and 4 * 4 IDCT / downsampling is performed for 8 * 8 blocks of BY, IC, PC, and BC.

This is done by IDCT conversion information written and recorded in the ROMs 801-804 corresponding to each case, and is simply achieved by switching control of the multiplexers 826 and 828 in response to each case.

That is, in case of receiving an SDTV image, the first multiplexer 826 performs 8-point output, and in case of receiving an HDTV image, the first multiplexer 826 outputs 4-point downsampled vertically with respect to IY and PY data by the second multiplexer 828. (1D-IDCT / downsampling), and performs four-point downsampled horizontally / vertically for BY, IC, PC, and BC data (2D-IDCT / downsampling, 1D- as shown in FIG. 8). Go through the IDCT circuit once more).

According to the present invention, when a high-definition picture that affects the image quality of a reproduced image is received and processed in an SDTV receiver using MPEG2 when downsampling to include more information than a picture that is not important, The IDCT / downsampler of each line performing IDCT / downsampling in different sizes can be integrated and shared as one.

Claims (3)

Picture data is processed in units of blocks, and data processed in units of blocks is classified so that the data of the first group is M * N, and the data of the second group is K * L (M * N > K * L). In the digital image decoder which performs IDCT and downsampling (filtering and decimation) in size, Computing means for processing IDCT or IDCT / downsampling of block unit data; A storage means for storing an IDCT conversion coefficient value corresponding to a control signal by inputting a picture size, an input of a frame rate, a scanning method, a reception mode, etc., and outputting the stored information corresponding to the input signal; Control means for controlling the operation of said computing means by said control signal to select IDCT or IDCT / downsampling and to selectively output the stored value of said storage means; And an n-point IDCT mode and an n-point IDCT / downsampling mode, including the discrete discrete cosine converter of the digital TV receiver decoder. The picture data is processed in block units (8 * 8), and the data processed in block units is divided into IDCT and 8-sized data in the first group, and 4 * 4 sized data in the second group. In the digital video decoder to perform downsampling (filtering and decimation), An operation that performs IDCT or IDCT / downsampling operation by inputting ROM (ROM) in which the IDCT coefficient values for each of the above cases are stored, and 8DCT coefficient as input, and data of the ROM (ROM) for each case as input. And circuits 805-824 and switching means 826, 828 for selecting an output value of the arithmetic circuit in response to a picture, frame rate, scanning method, and reception mode, to perform 1D-IDCT / downsampling. Inverse Discrete Cosine Transform of Digital TV Receive Decoder Device. The inverse discrete cosine converter of claim 2, wherein the 1D-IDCT / downsampler is cascaded to perform 2D-IDCT / downsampling on data of a second group.

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