KR960008524B1 - Multi-layer metal-wiring method - Google Patents

Multi-layer metal-wiring method Download PDF

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Publication number
KR960008524B1
KR960008524B1 KR93012888A KR930012888A KR960008524B1 KR 960008524 B1 KR960008524 B1 KR 960008524B1 KR 93012888 A KR93012888 A KR 93012888A KR 930012888 A KR930012888 A KR 930012888A KR 960008524 B1 KR960008524 B1 KR 960008524B1
Authority
KR
South Korea
Prior art keywords
layer
metal layer
flattening
wiring method
metal
Prior art date
Application number
KR93012888A
Other languages
Korean (ko)
Other versions
KR950004497A (en
Inventor
Hyung-Sik Ryu
Chang-Jin Ko
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Priority to KR93012888A priority Critical patent/KR960008524B1/en
Publication of KR950004497A publication Critical patent/KR950004497A/en
Application granted granted Critical
Publication of KR960008524B1 publication Critical patent/KR960008524B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The multi-layer metal wiring method comprises the steps of: formating a barrier layer on a surface where steps are formed by a device separating layer and a poly gate; stacking first aluminum metal layer and a flattening metal layer, and applying a PR on the surface; flattening the upper surface of the PR layer and the flattening metal surface by etching with a same ratio(etch back process); depositing second aluminum metal layer; formating a low metal wiring layer by etching a part of the second aluminum metal layer, metal layer and first aluminum metal layer (patterning process); thereby increasing a step coverage of the device.
KR93012888A 1993-07-09 1993-07-09 Multi-layer metal-wiring method KR960008524B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93012888A KR960008524B1 (en) 1993-07-09 1993-07-09 Multi-layer metal-wiring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93012888A KR960008524B1 (en) 1993-07-09 1993-07-09 Multi-layer metal-wiring method

Publications (2)

Publication Number Publication Date
KR950004497A KR950004497A (en) 1995-02-18
KR960008524B1 true KR960008524B1 (en) 1996-06-26

Family

ID=19359004

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93012888A KR960008524B1 (en) 1993-07-09 1993-07-09 Multi-layer metal-wiring method

Country Status (1)

Country Link
KR (1) KR960008524B1 (en)

Also Published As

Publication number Publication date
KR950004497A (en) 1995-02-18

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