KR100336654B1 - Method for forming stacked via hole in semiconductor device - Google Patents

Method for forming stacked via hole in semiconductor device Download PDF

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Publication number
KR100336654B1
KR100336654B1 KR1019950059661A KR19950059661A KR100336654B1 KR 100336654 B1 KR100336654 B1 KR 100336654B1 KR 1019950059661 A KR1019950059661 A KR 1019950059661A KR 19950059661 A KR19950059661 A KR 19950059661A KR 100336654 B1 KR100336654 B1 KR 100336654B1
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South Korea
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forming
via hole
interlayer insulating
stacked via
insulating film
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KR1019950059661A
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Korean (ko)
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KR970053548A (en
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정병현
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a stacked via hole in a semiconductor device is provided to be capable of simplifying manufacturing processes and improving integration degree. CONSTITUTION: The first interlayer dielectric(3) is formed on a semiconductor substrate(1) having a junction layer(2). The first wiring pattern(7) is formed on the first interlayer dielectric. The second interlayer dielectric(8) is formed on the resultant structure. A stacked via hole(13) is then formed by sequentially etching the second interlayer dielectric(8), the first wiring pattern(7) and the first interlayer dielectric(3). After forming a diffusion barrier layer on the resultant structure, a metal film is filled into the stacked via hole. Then, the second wiring pattern is formed on the resultant structure.

Description

반도체소자의 적층 비아홀 형성방법Method of forming stacked via holes in semiconductor device

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 제2 층간절연막과,금속배선층 및 제1 층간절연막을 순차적으로 식각하여 적층비아홀을 형성하고, 금속막으로 적층 비아홀(via hole)을 동시에 메립시키므로써, 소자의 집적도를 향상할 수 있는 반도체소자의 적층 비아홀형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the second interlayer insulating film, the metal wiring layer, and the first interlayer insulating film are sequentially etched to form stacked via holes, and the stacked via holes are simultaneously filled with a metal film. In addition, the present invention relates to a method for forming a stacked via hole of a semiconductor device capable of improving the integration degree of the device.

제 1A 도 내지 제 1N 도는 종래의 적층 비아 형성방법의 제조 공정도이다.1A to 1N are manufacturing process diagrams of a conventional method for forming a stacked via.

제 1A 도를 참조하면, 반도체기판(1)의 상부 표면에 접촉저항을 줄이기 위한 접합층(2)을 형성한다.Referring to FIG. 1A, a bonding layer 2 is formed on the upper surface of the semiconductor substrate 1 to reduce contact resistance.

그 다음, 상기 반도체기판(1)의 표면에 제1 층간절연막(3)을 형성한다.Next, a first interlayer insulating film 3 is formed on the surface of the semiconductor substrate 1.

제 1B 도를 참조하면, 상기 제1 층간절연막(3)의 상부에 제1 감광막을 도포한 후, 노광 및 현상 공정으로 콘택홀을 형성하기 위한 제1 감광막패턴(도시안함)을 형성한다.Referring to FIG. 1B, a first photosensitive film is coated on the first interlayer insulating film 3, and then a first photosensitive film pattern (not shown) is formed to form contact holes in an exposure and development process.

그 다음, 상기 제1 감광막패턴을 마스크로 상기 제1 층간절연막(3)을 반도체기판(1)이 노출될 때까지 식각하여 콘택홀(4)을 형성한다.Next, the first interlayer insulating layer 3 is etched using the first photoresist pattern as a mask until the semiconductor substrate 1 is exposed to form a contact hole 4.

그 다음, 상기 제2 감광막패턴을 제거한다.Next, the second photoresist pattern is removed.

제 1C 도를 참조하면, 상기 구조의 전 표면에 화학기상증착법으로 100 내지 300 Å 두께의 제1 확산제어막(5), 예를들어 질화티타늄막을 형성한다.Referring to FIG. 1C, a first diffusion control film 5, for example, a titanium nitride film, having a thickness of 100 to 300 Å is formed on the entire surface of the structure by chemical vapor deposition.

제 1D 도를 참조하면, 상기 구조의 전 표면에 제1 금속막(6), 예를 들어 텅스텐을 형성하되, 콘택홀(3)이 충분히 메립되도록 형성한다.Referring to FIG. 1D, a first metal film 6, for example tungsten, is formed on the entire surface of the structure, and the contact hole 3 is formed to be sufficiently filled.

제 1E 도를 참조하면, 상기 제1 금속막(6)을 반도체기판(1)이 노출될 때까지 평탄하게 식각한다.Referring to FIG. 1E, the first metal film 6 is etched flat until the semiconductor substrate 1 is exposed.

제 1F 도를 참조하면, 상기 구조의 전 표면에 제1 배선막(7)을 형성한다.Referring to FIG. 1F, the first wiring film 7 is formed on the entire surface of the structure.

제 1G 도를 참조하면, 상기 제1 배선막(7)을 식각하여 제1 배선막(7) 패턴을 형성한다.Referring to FIG. 1G, the first wiring layer 7 is etched to form a first wiring layer 7 pattern.

제 1H 도를 참조하면, 상기 구조의 전 표면에 제2 층간절연막(8)을 형성한다.Referring to FIG. 1H, a second interlayer insulating film 8 is formed on the entire surface of the structure.

제 1I 도를 참조하면, 상기 구조의 전 표면에 감광막을 도포한 후, 노광 및 현상 공정으로 비아홀(via hole)를 형성하기 위한 감광막패턴(도시안함)을 형성한다.Referring to FIG. 1I, after the photoresist film is applied to the entire surface of the structure, a photoresist pattern (not shown) for forming a via hole is formed by an exposure and development process.

그 다음, 상기 감광막패턴을 마스크로 상기 제2 층간절연막(8)을 제1 배선막(7) 패턴이 노출될 때까지 식각하여 비아홀(9)을 형성한다.Next, the second interlayer insulating film 8 is etched using the photosensitive film pattern as a mask until the first wiring film 7 pattern is exposed to form a via hole 9.

그 다음, 상기 감광막패턴을 제거한다.Then, the photoresist pattern is removed.

제 1J 도를 참조하면, 상기 구조의 전 표면에 화학기상증착법으로 100 내지 300 Å 두께의 제2 확산제어막(10), 예를 들어 질화티타늄막을 형성한다.Referring to FIG. 1J, a second diffusion control film 10, for example, a titanium nitride film, having a thickness of 100 to 300 Å is formed on the entire surface of the structure by chemical vapor deposition.

제 1K 도를 참조하면, 상기 구조의 전 표면에 제2 금속막(11), 예를들어, 텅스텐을 형성하되, 비아홀(10)이 충분히 메립되도록 형성한다.Referring to FIG. 1K, a second metal film 11, for example, tungsten, is formed on the entire surface of the structure, and the via hole 10 is formed to be sufficiently filled.

제 1L 도를 참조하면, 상기 제2 금속막(11)을 반도체기판(1)이 노출될 때까지 평탄하게 식각한다.Referring to FIG. 1L, the second metal layer 11 is etched flat until the semiconductor substrate 1 is exposed.

제 1M 도를 참조하면, 상기 구조의 전 표면에 제2 배선막(12)을 형성한다.Referring to FIG. 1M, the second wiring film 12 is formed on the entire surface of the structure.

제 1N 도를 참조하면, 상기 제2 배선막(12)을 식각하여 제2 배선막(12) 패턴을 형성한다.Referring to FIG. 1N, the second wiring layer 12 is etched to form a second wiring layer 12 pattern.

그러나, 상기와 같은 종래의 콘택홀과 비아홀이 같은 위치에 형성되는 반도체소자의 적층 비아 형성방법은 금속막으로 콘택홀을 메립한 후, 그 상부에 배선막을 형성시켜 주는 제작과정을 두번에 걸쳐 진행하기 때문에 공정순서가 복잡하고, 제작단가가 높은 문제점이 있다.However, according to the conventional method of forming a stacked via of a semiconductor device in which a contact hole and a via hole are formed at the same position, a manufacturing process of filling a contact hole with a metal film and then forming a wiring film thereon is performed twice. Therefore, there is a problem in that the process sequence is complicated and the manufacturing cost is high.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 본 발명은 제1 층간절연막과, 제1 배선막 및 제2 층간절연막을 차례로 증착한 후, 상기 제2 층간절연막, 제1 배선막 및 제1 층간절연막을 순차적으로 식각하여 적층 비아홀을 형성하고, 상기 적층 비아홀을 금속막으로 메운 후, 제2 배선막을 형성하므로써, 공정을 단순화할 수 있고, 미세한 크기의 콘택홀과 비아홀을 동시에 메립할 수 있는 반도체소자의 적층 비아홀 형성방법을 제공함에 그 목적이 있다.The present invention is to solve the above problems, the present invention after depositing the first interlayer insulating film, the first wiring film and the second interlayer insulating film in order, the second interlayer insulating film, the first wiring film and the first By sequentially etching the interlayer insulating film to form a stacked via hole, filling the laminated via hole with a metal film, and then forming a second wiring film, the process can be simplified, and fine contact holes and via holes can be simultaneously filled. It is an object of the present invention to provide a method for forming a stacked via hole of a semiconductor device.

상기 목적을 달성하기 위하여 본 발명의 반도체소자의 적층비아홀 형성방법은 반도체기판의 상부 표면에 접합층을 형성하는 단계와,In order to achieve the above object, a method of forming a stacked via hole of a semiconductor device according to the present invention includes forming a bonding layer on an upper surface of a semiconductor substrate;

상기 반도체기판의 표면에 제1 층간절연막을 형성하는 단계와,Forming a first interlayer insulating film on the surface of the semiconductor substrate;

상기 제1 층간절연막의 상부에 제1 배선막패턴을 형성하는 단계와,Forming a first wiring film pattern on the first interlayer insulating film;

상기 구조의 전 표면에 제2 층간절연막을 형성하는 단계와,Forming a second interlayer insulating film on the entire surface of the structure;

제2 층간절연막, 제1 배선막패턴 및 제1 층간절연막을 식각하여 적층 비아홀을 형성하는 단계와,Etching the second interlayer insulating film, the first wiring film pattern, and the first interlayer insulating film to form a stacked via hole;

상기 구조의 전 표면에 확산제어막을 형성하는 단계와,Forming a diffusion control film on the entire surface of the structure;

적층비아홀이 충분히 메립되도록 금속층을 형성한 후 식각하되, 제2 층간절연막이 노출될 때까지 평탄하게 식각하게 식각하는 단계와,Forming a metal layer so as to sufficiently fill the stacked via holes, and etching the same, but etching the layered layer until the second interlayer dielectric layer is exposed;

상기 구조의 전 표면에 제2 배선막패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.And forming a second wiring film pattern on the entire surface of the structure.

이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 하자.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제 2A 도 내지 제 2J 도는 본 발명의 실시예에 따른 반도체소자의 적층비아 형성방법의 제조 공정도이다.2A through 2J are manufacturing process diagrams of a method of forming a stacked via of a semiconductor device according to an exemplary embodiment of the present invention.

제 2A 도를 참조하면, 반도체기판(1)의 상부 표면에 접촉저항을 줄이기 위한 접합층(2)을 형성한다.Referring to FIG. 2A, a bonding layer 2 is formed on the upper surface of the semiconductor substrate 1 to reduce contact resistance.

그 다음, 상기 반도체기판(1)의 표면에 제1 층간절연막(3)을 형성한다.Next, a first interlayer insulating film 3 is formed on the surface of the semiconductor substrate 1.

제 2B 도를 참조하면, 상기 제1 층간절연막(3)의 상부에 제1 배선막(7)을 형 성한다.Referring to FIG. 2B, a first wiring film 7 is formed on the first interlayer insulating film 3.

제 2C 도를 참조하면, 상기 제1 배선막(7)을 식각하여 제1 배선막(7) 패턴을 형성한다.Referring to FIG. 2C, the first wiring layer 7 is etched to form a first wiring layer 7 pattern.

제 2D 도를 참조하면, 상기 구조의 전 표면에 제2 층간절연막(8)을 형성한다.Referring to FIG. 2D, a second interlayer insulating film 8 is formed on the entire surface of the structure.

제 2E 도를 참조하면, 상기 구조의 전 표면에 감광막을 도포한 후, 비아홀(9)을 형성하기 위한 마스크를 사용한 노광 및 현상 공정으로 감광막 패턴(도시 안함)을 형성한다.Referring to FIG. 2E, after the photoresist is applied to the entire surface of the structure, a photoresist pattern (not shown) is formed by an exposure and development process using a mask for forming the via hole 9.

그 다음, 상기 감광막패턴을 사용하여 상기 제2 층간절연막(8), 제1 금속막(7), 제1 층간절연막(3)을 차례로 식각하되, 접합층(2)이 형성된 반도체기판이 노출될 때까지 식각하여 제2 층간절연막(8) 패턴과, 제1 금속막(7) 패턴과, 제1층간절연막(3) 패턴을 형성하여 적층비아홀(13)을 형성한다.Next, the second interlayer insulating film 8, the first metal film 7, and the first interlayer insulating film 3 are sequentially etched using the photosensitive film pattern, and the semiconductor substrate on which the bonding layer 2 is formed is exposed. By etching until the second interlayer insulating film 8 pattern, the first metal film 7 pattern, and the first interlayer insulating film 3 pattern are formed, the stacked via holes 13 are formed.

그 다음, 상기 감광막패턴을 제거한다.Then, the photoresist pattern is removed.

제 2F 도를 참조하면, 상기 구조의 전 표면에 화학기상증착법으로 100 내지 300 Å 두께의 확산제어막(5), 예를 들어 질화티타늄막을 형성한다.Referring to FIG. 2F, a diffusion control film 5, for example, a titanium nitride film, is formed on the entire surface of the structure by chemical vapor deposition.

제 2G 도를 참조하면, 상기 구조의 전 표면에 제1 금속층(6), 예를들어 텅스텐을 메립하되, 적층비아홀(13)이 충분히 메립되도록 형성한다.Referring to FIG. 2G, the first metal layer 6, for example tungsten, is embedded in the entire surface of the structure, and the stacked via holes 13 are formed to be sufficiently filled.

제 2H 도를 참조하면, 상기 구조의 전 표면에 상기 제1 금속층(6)을 제2 층간절연막(8)이 노출될 때까지 평탄하게 식각한다.Referring to FIG. 2H, the first metal layer 6 is etched flat on the entire surface of the structure until the second interlayer insulating film 8 is exposed.

제 2I 도를 참조하면, 상기 구조의 전 표면에 제2 배선막(12), 예를들어 알루미늄을 스퍼터링방법으로 형성한다.Referring to FIG. 2I, a second wiring film 12, for example aluminum, is formed on the entire surface of the structure by the sputtering method.

제 2J 도를 참조하면, 상기 제2 배선막(12)을 식각하여 제2 배선막(12) 패턴을 형성한다.Referring to FIG. 2J, the second wiring layer 12 is etched to form a second wiring layer 12 pattern.

참고로, 상기 제2G도 내지 제2I도 에서 진행하는 공정 대신에 화학기상증착법으로 구리나 알루미늄을 상기 적층비아홀(13)에 충분히 메립하고, 계속하여 상기 구리나 알루미늄으로 제2 배선막을 형성할 수 도 있다.For reference, instead of the process proceeding in FIGS. 2G to 2I, copper or aluminum may be sufficiently embedded in the laminated via hole 13 by chemical vapor deposition, and a second wiring film may be subsequently formed of the copper or aluminum. There is also.

상술한 바와 같이 본 발명의 반도체소자의 적층비아 형성 방법은 제2 층간 절연막과, 금속배선층 및 제1 층간절연막을 순차적으로 식각해 준 다음에 금속막으로 콘택홀(contact hole)과 비아홀(via hole)을 동시에 메립시키므로써, 공정을 단순하게 하는 이점이 있으며, 소자의 집적도를 향상할 수 있는 이점이 있다.As described above, in the method of forming a stacked via of the semiconductor device according to the present invention, the second interlayer insulating film, the metal wiring layer, and the first interlayer insulating film are sequentially etched, and then contact holes and via holes are formed of a metal film. By simultaneously filling), there is an advantage of simplifying the process, there is an advantage to improve the integration of the device.

제 1A 도 내지 제 1N 도는 종래의 실시예에 따른 반도체소자의 적층 비아홀 제조 공정도.1A through 1N illustrate a process of manufacturing a stacked via hole of a semiconductor device according to a conventional embodiment.

제 2A 도 내지 제 2J 도는 본 발명의 실시예에 따른 반도체소자의 적층 비아홀 제조 공정도.2A to 2J are process charts for manufacturing a stacked via hole of a semiconductor device according to an embodiment of the present invention.

※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing

1 : 반도체 기판 2 : 접합층1 semiconductor substrate 2 bonding layer

3 : 제1 층간절연막 4 : 콘택홀3: first interlayer insulating film 4: contact hole

5 : 제1 확산방지층 6 : 제1 금속층5: first diffusion barrier layer 6: first metal layer

7 : 제1 배선막 8 : 제2 층간절연막7: first wiring film 8: second interlayer insulating film

9 : 비아홀 10 : 제2 확산방지층9: via hole 10: second diffusion barrier layer

11 : 제2 금속층 12 : 제2 배선막11 second metal layer 12 second wiring film

Claims (8)

반도체기판의 상부 표면에 접합층을 형성하는 단계와,Forming a bonding layer on the upper surface of the semiconductor substrate; 상기 반도체기판의 표면에 제1 층간절연막을 형성하는 단계와,Forming a first interlayer insulating film on the surface of the semiconductor substrate; 상기 제1 층간절연막의 상부에 제1 배선막패턴을 형성하는 단계와,Forming a first wiring film pattern on the first interlayer insulating film; 상기 구조의 전 표면에 제2 층간절연막을 형성하는 단계와,Forming a second interlayer insulating film on the entire surface of the structure; 제2 층간절연막, 제1 배선막패턴 및 제1 층간절연막을 식각하여 적층 비아홀을 형성하는 단계와,Etching the second interlayer insulating film, the first wiring film pattern, and the first interlayer insulating film to form a stacked via hole; 상기 구조의 전 표면에 확산제어막을 형성하는 단계와,Forming a diffusion control film on the entire surface of the structure; 적층비아홀이 충분히 메립되도록 금속층을 형성한 후 식각하되, 제2 층간절연막이 노출될 때까지 평탄하게 식각하는 단계와,Forming a metal layer so as to sufficiently fill the stacked via holes, and etching the same, until the second interlayer insulating film is exposed; 상기 구조의 전 표면에 제2 배선막패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도제소자의 적층 비아홀 형성방법.And forming a second wiring film pattern on the entire surface of the structure. 제 1 항에 있어서,The method of claim 1, 상기 확산제어막으로 질화티타늄을 이용하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.Titanium nitride is used as the diffusion control layer. 제 1 항에 있어서,The method of claim 1, 상기 확산제어막은 화학기상증착법으로 100 내지 300 Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.The diffusion control film is a method of forming a stacked via hole of a semiconductor device, characterized in that formed by the chemical vapor deposition method to 100 to 300 Å thickness. 제 1 항에 있어서,The method of claim 1, 상기 금속층으로 텅스텐을 사용하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법Method of forming a stacked via hole in a semiconductor device, characterized in that tungsten is used as the metal layer 제 1 항에 있어서,The method of claim 1, 상기 제2 배선막으로 알루미늄을 사용하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.And using aluminum as the second wiring layer. 제 1 항에 있어서,The method of claim 1, 상기 제2 배선막패턴을 스퍼터링방법으로 형성하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.And forming the second wiring film pattern by a sputtering method. 제 1 항에 있어서,The method of claim 1, 상기 적층비아홀이 충분히 메립되도록 금속층을 형성한 후 식각하되, 제2 층간절연막이 노출될 때까지 평탄하게 식각하게 식각하는 단계와,Forming a metal layer so as to sufficiently fill the stacked via holes, and then etching the same, but etching the layered via holes until the second interlayer dielectric layer is exposed; 상기 구조의 전 표면에 제2 배선막패턴을 형성하는 단계를 포함하는 대신에 화학기상증착법으로 금속층을 상기 적층비아홀에 충분히 메립하고, 계속하여 상기 금속층으로 제2 배선막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.Instead of forming a second wiring film pattern on the entire surface of the structure, by filling a metal layer in the laminated via hole by chemical vapor deposition, and subsequently forming a second wiring film by the metal layer. A method of forming a stacked via hole in a semiconductor device. 제 6 항에 있어서,The method of claim 6, 상기 금속층으로 구리 또는 알루미늄을 사용하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.Laminated via hole forming method of a semiconductor device, characterized in that the metal layer using copper or aluminum.
KR1019950059661A 1995-12-27 1995-12-27 Method for forming stacked via hole in semiconductor device KR100336654B1 (en)

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US7531373B2 (en) 2007-09-19 2009-05-12 Micron Technology, Inc. Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531373B2 (en) 2007-09-19 2009-05-12 Micron Technology, Inc. Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry

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