KR960002778B1 - Dram cell manufacturing method - Google Patents
Dram cell manufacturing method Download PDFInfo
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- KR960002778B1 KR960002778B1 KR1019920012596A KR920012596A KR960002778B1 KR 960002778 B1 KR960002778 B1 KR 960002778B1 KR 1019920012596 A KR1019920012596 A KR 1019920012596A KR 920012596 A KR920012596 A KR 920012596A KR 960002778 B1 KR960002778 B1 KR 960002778B1
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- KR
- South Korea
- Prior art keywords
- forming
- polysilicon
- oxide film
- film
- storage node
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 238000003860 storage Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract 4
- 238000005530 etching Methods 0.000 claims abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1도는 종래 디램셀의 공정단면도.1 is a process cross-sectional view of a conventional DRAM cell.
제2도는 본 발명 디램셀의 공정단면도.2 is a process cross-sectional view of the DRAM cell of the present invention.
제3도는 제2g도의 A-A선 단면도.3 is a cross-sectional view taken along the line A-A of FIG. 2g.
제4도는 제2c도의 사시도.4 is a perspective view of FIG. 2C.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 기판 21,29 : 산화막20: substrate 21,29: oxide film
22,28 : 질화막 23 : 실리콘22,28: nitride film 23: silicon
24 : 게이트 25 : 측벽24: gate 25: side wall
26 : N+영역 27 : 비트라인26: N + area 27: bit line
30 : 노드용 폴리실리콘 31 : 플레이트용 폴리실리콘30 polysilicon for nodes 31 polysilicon for plates
본 발명은 디램셀의 제조방법에 관한 것으로, 특히 커패시터의 표면적을 증가시키기에 적당하도록 한 것이다.The present invention relates to a method for manufacturing a DRAM cell, and is particularly suitable to increase the surface area of a capacitor.
종래의 디램셀 제조공정은 제1a도에 도시된 바와같이 p형 실리콘기판(1) 위에 로코스 공정을 이용한 필드산화막(2)을 형성시켜 먼저 필드영역과 액티브영역을 구분한다.In the conventional DRAM cell manufacturing process, as shown in FIG. 1A, the field oxide film 2 is formed on the p-type silicon substrate 1 using the LOCOS process to first distinguish the field region from the active region.
그리고 상기 액티브 영역에 게이트 산화막을 성장시키고 폴리실리콘을 증착한 후 에치(Etch)하여 게이트(3)를 형성한다.A gate oxide film is grown in the active region, polysilicon is deposited, and then etched to form a gate 3.
다음에 상기 게이트(3)를 형성한다.Next, the gate 3 is formed.
다음에 상기 게이트(3) 측면에 산화막으로 측벽(4)을 형성하고 이온 주입을 실시하여 N+영역(5)을 형성한다.Next, the sidewall 4 is formed of an oxide film on the side of the gate 3 and ion implantation is performed to form the N + region 5.
이 상태에서 다시 폴리실리콘을 증착하고 에치하여 비트라인(6)을 만든다.In this state, polysilicon is deposited and etched again to form the bit line 6.
또한, 1b도와 같이 웨이퍼 전면에 산화막(7), 질화막(8), 산화막(9)을 차례로 증착하고 마스킹 공정에 의해 노드 콘택을 형성한 후 스토리지 노드용 폴리실리콘(10)을 만든다.Further, as shown in FIG. 1B, an oxide film 7, a nitride film 8, and an oxide film 9 are sequentially deposited on the wafer, and a node contact is formed by a masking process to form a polysilicon 10 for a storage node.
이어서 1c도와 같이 상기 질화막(8)을 에치 스톱 포인트로 하여 산화막(9)을 제거한 다음 드러난 스토리지 노드용 폴리실리콘(10)에 1d도와 같이 커패시터 절연막(도면에 도시되지 않음)을 형성하고 플레이트용 폴리실리콘(11)을 증착한다.Subsequently, the oxide film 9 is removed using the nitride film 8 as an etch stop point as shown in 1c, and then a capacitor insulating film (not shown) is formed on the exposed polysilicon 10 for storage nodes, as shown in 1d. Silicon 11 is deposited.
그러나, 상기와 같은 종래 기술에 있어서는 고집적화 할수록 셀 사이즈가 줄어들게 되어 셀 커패시터가 충분한 용량을 유지하지 못하게 되므로 이러한 용량을 유지하려면 노드용 폴리실리콘(10)의 표면적이 충분히 커야하나 표면적 확보에 한계가 있다.However, in the prior art as described above, the cell size decreases as the integration becomes higher, and thus the cell capacitor does not maintain sufficient capacity. However, the surface area of the polysilicon 10 for nodes must be large enough to maintain such capacity, but there is a limit in securing the surface area. .
본 발명은 이와같은 종래의 결점을 해결하기 위한 것으로 커패시터의 표면적을 증가시킬 수 있는 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional drawback, and an object thereof is to provide a method for increasing the surface area of a capacitor.
이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제2도 내지 제4도에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to FIGS. 2 to 4.
먼저 제2도는 본 발명의 공정단면도로 2a도와 같이 p형 기판(20) 위에 산화막 (21), 질화막(22)을 차례로 형성하고 2b도와 같이 마스킹 공정에 의해 산화막(21)과 질화막(22)을 선택적 에치하여 에치되지 않은 부분을 필드영역으로 한정한다.First, in FIG. 2, the oxide film 21 and the nitride film 22 are sequentially formed on the p-type substrate 20 as shown in FIG. 2a, and the oxide film 21 and the nitride film 22 are formed by a masking process as shown in FIG. 2b. Selectively etch to limit the non-etched part to the field area.
그리고 2c도와 같이 상기 에치된 부분, 즉 액티브 영역에 선택적 에피택시를 이용하여 실리콘(23)을 성장시키면 p형 기판(20) 위에 성장된 실리콘(3)으로 인해 액티브 영역이 필드 영역보다 높아지게 된다.As shown in FIG. 2C, when the silicon 23 is grown using the selective epitaxy on the etched portion, that is, the active region, the active region becomes higher than the field region due to the silicon 3 grown on the p-type substrate 20.
이 상태에서 상기 액티브 영역 위에 게이트 산화막을 성장시키고 그 위에 폴리실리콘을 증착한 후 에치하여 게이트(24)를 만든다.In this state, a gate oxide film is grown on the active region, polysilicon is deposited thereon, and then etched to form a gate 24.
다음에 산화막을 증착하고 비등방성 에치하여 게이트(24) 측면에 측벽(25)을 형성한 후 이온을 주입하여 N+영역(26)을 만든다.Next, an oxide film is deposited and anisotropically etched to form sidewalls 25 on the side of the gate 24, and then ions are implanted to form the N + region 26.
이어서 2d도와 같이 폴리실리콘을 증착하고 에치하여 비트라인(27)을 형성한 후 절연막으로 질화막(28)을 증착하여 에치 스톱 포인트 역할을 하게 하며 웨이퍼 전표면에 산화막(29)을 증착한다.Subsequently, polysilicon is deposited and etched to form a bit line 27 as shown in FIG. 2d, and then a nitride layer 28 is deposited using an insulating layer to serve as an etch stop point, and an oxide layer 29 is deposited on the entire surface of the wafer.
또한 2e도와 같이 N+영역(26)과 필드산화막(21) 일부분을 포함한 부분에 노드용 콘택을 마스킹 공정에 의해 형성하고 스토리지 노드용 폴리실리콘(27)을 증착한다.Also, as shown in FIG. 2E, a node contact is formed in a portion including the N + region 26 and a part of the field oxide film 21 by a masking process, and the polysilicon 27 for the storage node is deposited.
그리고 2f도와 같이 상기 질화막(28)을 에치 스톱 포인트로 하여 산화막(29)을 제거한 후 2g도와 같이 드러난 노드용 폴리실리콘(30)에 커패시터 절연막을 형성시키고 플레이트용 폴리실리콘(31)을 증착한다.After removing the oxide film 29 using the nitride film 28 as an etch stop point as shown in FIG. 2f, a capacitor insulating film is formed on the polysilicon 30 for nodes exposed as shown in 2g and the polysilicon 31 for a plate is deposited.
상기 2g도에서 A-A선 단면으로 보면 제3도와 같이 나타나며 제4도는 상기 제2도의 2c도부분을 사시도로 나타낸 것이다.A cross-sectional view taken along line A-A in FIG. 2g shows a third view, and FIG. 4 shows a perspective view of a portion 2c of FIG.
이상에서 설명한 바와같은 본 발명은 액티브 영역에 실리콘(23)을 성장시키고 그 위에 커패시터를 형성시키므로 커패시터의 용량을 증가시킬 수 있는 효과가 있다.As described above, since the silicon 23 is grown in the active region and a capacitor is formed thereon, the capacity of the capacitor can be increased.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920012596A KR960002778B1 (en) | 1992-07-15 | 1992-07-15 | Dram cell manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920012596A KR960002778B1 (en) | 1992-07-15 | 1992-07-15 | Dram cell manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940003027A KR940003027A (en) | 1994-02-19 |
| KR960002778B1 true KR960002778B1 (en) | 1996-02-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920012596A KR960002778B1 (en) | 1992-07-15 | 1992-07-15 | Dram cell manufacturing method |
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|---|---|
| KR (1) | KR960002778B1 (en) |
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1992
- 1992-07-15 KR KR1019920012596A patent/KR960002778B1/en not_active IP Right Cessation
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| KR940003027A (en) | 1994-02-19 |
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