KR940009639B1 - Manufacturing method and structure of highly integrated memory cell capacitor - Google Patents

Abstract

The high integration memory cell capacitor is disclosed in which a groove is formed on a bit line, a node polysilicon is formed on the right and left of the groove to be connected to a node polysilicon formed on the side of a pillar placed on the groove, and hemispherical grain polysilicon is formed on the right and left of the groove, thereby increasing the capacitance of the node capacitor.

Description

Manufacturing method and structure of high density memory cell capacitor

1 is a method and structure diagram of a conventional memory cell capacitor manufacturing method.

2 is a method and structure diagram of a memory cell capacitor manufacturing method of the present invention.

* Explanation of symbols for main parts of the drawings

21 silicon substrate 22 gate

23: oxide film 24: polysilicon

25 side wall 26 dielectric film

27: nitride film 28: selective polysilicon

29: nitride film 30: oxide film

31 polysilicon for node 32 dielectric film

33: Plate

The present invention relates to a method and a structure for manufacturing a highly integrated memory cell capacitor, and in particular, to form a hemispherical node capacitor on a gated gate structure and to increase the capacity of a node and plate capacitor using a polysilicon monolayer when forming a pillar, and a method thereof. It's about structure.

Referring to Figure 1 attached to a conventional capacitor manufacturing method as follows.

First, as shown in FIG. 1A, the gate 2 is formed on the silicon substrate 1 with a word line, the oxide film 3 is coated, and a sidewall is formed. Thereafter, polysilicon 4 and tungsten silicide 5 are formed as shown in FIG. 1B, the oxide film 6 is coated, and sidewalls are formed again. Subsequently, as in the 1c diagram, the nitride film 7 and the oxide film 8 are formed and etched to form pillars on the oxide film 6 above the tungsten silicide 5. Subsequently, as shown in the 1d diagram, the polysilicon 9 for the node capacitor is applied in a thin layer, the oxide film 10 is applied, and then etched back until the oxide film 8 appears. Thereafter, the oxide film 8 is wet-etched and removed as in the 1e chart, and Ta ₂ O ₃ is coated as the dielectric film 11 and tungsten is deposited as the plate 12, as in the 1f chart, thereby completing the capacitor.

Capacitors manufactured in this conventional manner are limited in capacity and therefore not suitable for highly integrated cells.

Therefore, in the present invention, the gate structure is made into a cut-off type, a hemispherical node capacitor is formed thereon, and a pillar is formed thereon, thereby increasing the capacity of the capacitor.

Hereinafter, a method of manufacturing a capacitor of the present invention will be described with reference to FIG. 2.

First, as shown in FIG. 2A, a gate oxide film is grown on the silicon substrate 21, and then polysilicon is applied to first pattern the gate using a first mask, and the gate is formed using a second mask that is relatively smaller than the first mask. Differential patterning forms the " ㅗ " shaped gate 22. As shown in FIG.

Subsequently, as shown in FIG. 2B, an oxide film 23 is covered on the previously formed gate 22 to form sidewalls. Subsequently, as shown in FIG. 2C, a source / drain is formed by ion implantation, polysilicon 24 is applied to form a bit line, and heat treated at about 500 to 600 ° C. in a vibration state to form a hemispherical shape on the surface. Etch the polysilicon 24 at a predetermined portion of the upper portion of the gate using.

Subsequently, as shown in FIG. 2D, the bit line center portion is scraped off by a photo process by a predetermined width, the PR film is peeled off, and an oxide film sidewall 25 is formed on the side of the bit line on the gate.

Thereafter, as shown in FIG. 2E, the bit line is isolated by Ta ₂ O ₅ , which is the dielectric film 26, and the nitride film 27 is applied. Subsequently, the nitride film 27 is photoetched to form a columnar nitride film in the center of the upper groove of the bit line, and the bit line grooves on both sides of the columnar nitride film are selectively filled with polysilicon 28. Next, as shown in FIG. 2F, the nitride film 29 and the oxide film 30 are coated and then photoetched to form the nitride film and the oxide pillar on the nitride film 27. Subsequently, as in the second diagram, the polysilicon 31 for the node is applied, and PR is applied to the upper portion of the node polysilicon on the oxide film 30 and then etched back to remove the oxide film 39. Subsequently, as shown in FIG. 2h, Ta ₂ O ₅ is applied as the dielectric film 332 on the entire surface, and then tungsten for plate 33 is applied to complete the capacitor.

In the capacitor cell of the present invention manufactured as described above, the gate is formed in a “ㅗ” shape, a groove is formed in the upper part of the bit line, and node polysilicon is formed on the left and right sides of the groove except for the center separation insulating film. Hemispherical polysilicon is formed on top and left and right sides of the bit line grooves connected to the node polysilicon formed in the groove.

Since the capacitor formed by the manufacturing method and structure as described above is used, the following effects can be obtained.

First, since the "ㅗ" shaped gate structure and a part of the bit line are formed in a hemispherical structure, the capacity of the capacitor is increased by increasing the length of the node polysilicon and the plate.

Second, after the groove is formed by etching the bit line, the capacity of the node capacitor may be increased without using a pillar on the bit line using a nitride film and polysilicon.

Claims (2)

In the method of manufacturing a highly integrated memory cell capacitor, a gate oxide film is grown on a silicon substrate, followed by applying a gate polysilicon to pattern the gate first with a first mask, and first patterning with a second mask relatively smaller than the first mask. Patterning the gate to form a "ㅗ" -shaped gate by secondary patterning, forming an oxide film and a sidewall on the gate, applying polysilicon for the bit line, and heat-treating at a predetermined temperature in a vacuum state, thereby (B) forming a hemispherical shape, and forming a bit line by etching polysilicon for the bit line, then cutting a groove by a predetermined width at the center of the bit line and forming an oxide sidewall on the side of the bit line (c). A dielectric film is formed in the exposed bit line, and a nitride film is formed in the center of the groove formed in the bit line. (D) growing a selective polysilicon, forming a nitride film and an oxide pillar on the nitride film of the groove, applying polysilicon for the node on the front surface, and applying PR to apply the polysilicon and oxide layer for the node on the oxide pillar And removing (e) the dielectric film and the plate after the removal. In the highly integrated memory cell capacitor structure, a gate is formed in a “ㅗ” shape, a groove is formed in the upper part of the bit line, and node polysilicon is formed in the left and right portions except for the center isolation insulating film of the groove and is formed on the pillar side of the upper part of the groove. The high density memory cell capacitor structure is connected to the node polysilicon is formed, hemispherical polysilicon is formed on the upper left and right sides of the bit line groove.