KR960002671A - Method of forming interlayer insulating film of semiconductor device - Google Patents
Method of forming interlayer insulating film of semiconductor device Download PDFInfo
- Publication number
- KR960002671A KR960002671A KR1019940013893A KR19940013893A KR960002671A KR 960002671 A KR960002671 A KR 960002671A KR 1019940013893 A KR1019940013893 A KR 1019940013893A KR 19940013893 A KR19940013893 A KR 19940013893A KR 960002671 A KR960002671 A KR 960002671A
- Authority
- KR
- South Korea
- Prior art keywords
- metal layer
- sog film
- semiconductor device
- imo
- forming
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 다중 금속층 사이에 절연 및 평탄화를 위해 형성되는 금속층간 절연막의 형성방법에 관한 것으로, 스텝 커버리지 및 표면 평탄화를 향상시키기 위해 사용되는 SOG막이 금속층 형성시 수분을 방출하므로 인해 발생되는 소자의 전기적 특성저하를 개선하기 위해 SOG막 큐어링(Curing)후 SOG막 제거용 마스크를 사용하여 하부 금속층 양측의 SOG막을 블랭켓 식각(Blanket Etch)방법에 의해 상기 하부금속층 표면까지 제거하고 상기 하부 금속층 상부의 SOG막 및 제1IMO을 에치 백(Etch Back) 공정에 의해 순차적으로 제거시킨 다음 제2IMO을 형성시키므로써 금속층 및 SOG막과의 접촉이 방지되고 전자 및 스트레스의 이동을 감소시켜 소자의 전기적 특성을 향상시킬 수 있도록 한 반도체 소자의 다중 금속층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an intermetallic insulating film formed for insulation and planarization between multiple metal layers of a semiconductor device. In order to improve the electrical characteristics of the device, after the SOG film curing, the SOG film on both sides of the lower metal layer is removed to the surface of the lower metal layer by a blanket etching method by using a mask for removing the SOG film. The SOG film and the first IMO over the metal layer are sequentially removed by an etch back process to form a second IMO, thereby preventing contact with the metal layer and the SOG film and reducing the movement of electrons and stress, thereby reducing the electrical A method of forming a multi-metal layer of a semiconductor device to improve the characteristics.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2A 내지 제2D도는 본 발명에 따른 반도체 소자의 금속층간 절연막 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940013893A KR960002671A (en) | 1994-06-20 | 1994-06-20 | Method of forming interlayer insulating film of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940013893A KR960002671A (en) | 1994-06-20 | 1994-06-20 | Method of forming interlayer insulating film of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR960002671A true KR960002671A (en) | 1996-01-26 |
Family
ID=66686249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940013893A KR960002671A (en) | 1994-06-20 | 1994-06-20 | Method of forming interlayer insulating film of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960002671A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100751446B1 (en) * | 2000-07-21 | 2007-08-23 | 에스브이지 리도그래피 시스템즈, 아이엔씨. | High numerical aperture catadioptric lens |
-
1994
- 1994-06-20 KR KR1019940013893A patent/KR960002671A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100751446B1 (en) * | 2000-07-21 | 2007-08-23 | 에스브이지 리도그래피 시스템즈, 아이엔씨. | High numerical aperture catadioptric lens |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR960005870A (en) | Metal wiring formation method of semiconductor device | |
KR940022801A (en) | Contact formation method of semiconductor device | |
KR970072380A (en) | Semiconductor device and manufacturing method thereof | |
KR960002671A (en) | Method of forming interlayer insulating film of semiconductor device | |
KR970052439A (en) | Contact hole formation method of semiconductor device | |
KR960002486A (en) | Method of forming multiple metal layers in semiconductor devices | |
KR100208450B1 (en) | Method for forming metal wiring in semiconductor device | |
KR930014802A (en) | Method for manufacturing interlayer insulating layer between upper and lower conductive layers | |
KR960002644A (en) | Method of forming interlayer insulating film of semiconductor device | |
KR970052570A (en) | Planarization method of semiconductor device | |
KR970052386A (en) | Metal wiring formation method of semiconductor device | |
KR960019569A (en) | Semiconductor device manufacturing method | |
KR940012572A (en) | Contact Forming Method in Semiconductor Device | |
KR960002648A (en) | Method of forming interlayer insulating film of semiconductor device | |
KR970052381A (en) | Metal layer formation method of semiconductor device | |
KR970024006A (en) | Method of forming multi-layer metal wiring of semiconductor device | |
KR930009024A (en) | Contact Forming Method of Semiconductor Device | |
KR940010366A (en) | Method for manufacturing contact hole of semiconductor device | |
KR960012324A (en) | Gate electrode contact of semiconductor device and manufacturing method thereof | |
KR970053587A (en) | A semiconductor device manufacturing method comprising a multilayer metal layer | |
KR960043116A (en) | Planarization method of semiconductor device | |
KR960026568A (en) | Device isolation insulating film manufacturing method of semiconductor device | |
KR940022854A (en) | Method of forming contact window of semiconductor device | |
KR970053558A (en) | Method for forming interlayer insulating film of semiconductor device | |
KR960026632A (en) | Method of forming multi-layer metal wiring of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |