KR960002671A - Method of forming interlayer insulating film of semiconductor device - Google Patents

Method of forming interlayer insulating film of semiconductor device Download PDF

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Publication number
KR960002671A
KR960002671A KR1019940013893A KR19940013893A KR960002671A KR 960002671 A KR960002671 A KR 960002671A KR 1019940013893 A KR1019940013893 A KR 1019940013893A KR 19940013893 A KR19940013893 A KR 19940013893A KR 960002671 A KR960002671 A KR 960002671A
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KR
South Korea
Prior art keywords
metal layer
sog film
semiconductor device
imo
forming
Prior art date
Application number
KR1019940013893A
Other languages
Korean (ko)
Inventor
장은미
육형선
백현철
김상익
구영모
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940013893A priority Critical patent/KR960002671A/en
Publication of KR960002671A publication Critical patent/KR960002671A/en

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Abstract

본 발명은 반도체 소자의 다중 금속층 사이에 절연 및 평탄화를 위해 형성되는 금속층간 절연막의 형성방법에 관한 것으로, 스텝 커버리지 및 표면 평탄화를 향상시키기 위해 사용되는 SOG막이 금속층 형성시 수분을 방출하므로 인해 발생되는 소자의 전기적 특성저하를 개선하기 위해 SOG막 큐어링(Curing)후 SOG막 제거용 마스크를 사용하여 하부 금속층 양측의 SOG막을 블랭켓 식각(Blanket Etch)방법에 의해 상기 하부금속층 표면까지 제거하고 상기 하부 금속층 상부의 SOG막 및 제1IMO을 에치 백(Etch Back) 공정에 의해 순차적으로 제거시킨 다음 제2IMO을 형성시키므로써 금속층 및 SOG막과의 접촉이 방지되고 전자 및 스트레스의 이동을 감소시켜 소자의 전기적 특성을 향상시킬 수 있도록 한 반도체 소자의 다중 금속층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an intermetallic insulating film formed for insulation and planarization between multiple metal layers of a semiconductor device. In order to improve the electrical characteristics of the device, after the SOG film curing, the SOG film on both sides of the lower metal layer is removed to the surface of the lower metal layer by a blanket etching method by using a mask for removing the SOG film. The SOG film and the first IMO over the metal layer are sequentially removed by an etch back process to form a second IMO, thereby preventing contact with the metal layer and the SOG film and reducing the movement of electrons and stress, thereby reducing the electrical A method of forming a multi-metal layer of a semiconductor device to improve the characteristics.

Description

반도체 소자의 금속층간 절연막 형성방법Method of forming interlayer insulating film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A 내지 제2D도는 본 발명에 따른 반도체 소자의 금속층간 절연막 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention.

Claims (1)

반도체 소자의 금속층간 절연막 형성방법에 있어서, 소자 내부 집적층이 형성되며 상부에 절연층(2)이 형성된 실리콘 기판(1)상에 제1금속층(3)을 형성하고 제1IMO(4)을 형성한 다음 SOG(5)를 도포하고 큐어링하여 평탄화시킨 후 감광막을 도포하고 패터닝하여 상기 제1금속층(3) 상부에 SOG막 제거용 마스크(11)를 형성시키는 단계와, 상기 단계로부터 블랭켓 식각방법에 의해 노출된 SOG막(5)을 상기 제1금속층(3)의 표면 높이까지 식각한 후 상기 SOG막 제거용 마스크(11)를 제거시키는 단계와, 상기 단계로부터 에치백 식각방법에 의해 상기 제1금속층(3) 상부에 잔류된 SOG막(5) 및 제1IMO(4)을 순차적으로 제거시킨 후 제2IMO(8)을 형성시키는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속층간 절연막 형성방법.In the method for forming an interlayer insulating film of a semiconductor device, a first metal layer 3 and a first IMO 4 are formed on a silicon substrate 1 having an internal integrated layer formed thereon and an insulating layer 2 formed thereon. After the SOG (5) is applied, cured and planarized, a photosensitive film is applied and patterned to form a SOG film removal mask (11) on the first metal layer (3), and the blanket etching from the step Etching the SOG film 5 exposed by the method to the surface height of the first metal layer 3, and then removing the SOG film removing mask 11; and by the etch back etching method from the step Forming a second IMO (8) after sequentially removing the SOG film (5) and the first IMO (4) remaining on the first metal layer (3). . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940013893A 1994-06-20 1994-06-20 Method of forming interlayer insulating film of semiconductor device KR960002671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940013893A KR960002671A (en) 1994-06-20 1994-06-20 Method of forming interlayer insulating film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940013893A KR960002671A (en) 1994-06-20 1994-06-20 Method of forming interlayer insulating film of semiconductor device

Publications (1)

Publication Number Publication Date
KR960002671A true KR960002671A (en) 1996-01-26

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Application Number Title Priority Date Filing Date
KR1019940013893A KR960002671A (en) 1994-06-20 1994-06-20 Method of forming interlayer insulating film of semiconductor device

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KR (1) KR960002671A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100751446B1 (en) * 2000-07-21 2007-08-23 에스브이지 리도그래피 시스템즈, 아이엔씨. High numerical aperture catadioptric lens

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100751446B1 (en) * 2000-07-21 2007-08-23 에스브이지 리도그래피 시스템즈, 아이엔씨. High numerical aperture catadioptric lens

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