KR960001779B1 - Dual port ram capable of input/output simultaneously on dual - Google Patents

Dual port ram capable of input/output simultaneously on dual Download PDF

Info

Publication number
KR960001779B1
KR960001779B1 KR93012135A KR930012135A KR960001779B1 KR 960001779 B1 KR960001779 B1 KR 960001779B1 KR 93012135 A KR93012135 A KR 93012135A KR 930012135 A KR930012135 A KR 930012135A KR 960001779 B1 KR960001779 B1 KR 960001779B1
Authority
KR
South Korea
Prior art keywords
output
dual
input
read enable
port ram
Prior art date
Application number
KR93012135A
Other languages
Korean (ko)
Other versions
KR950001762A (en
Inventor
Se-Jin Kang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to KR93012135A priority Critical patent/KR960001779B1/en
Publication of KR950001762A publication Critical patent/KR950001762A/en
Application granted granted Critical
Publication of KR960001779B1 publication Critical patent/KR960001779B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

a the latch unit operated by control signal, a first output buffer operated by a first read enable signal which is inputted from an input/output port of the first system, and which is connected to output of the latch unit; a second output buffer is connected to output of the latch unit and activated by the second read enable signal inputted from input/output port of second system; and the logic method which generates control signal with combination of the first and second write selecting signal. The output of the first output buffer is determined by the first read enable signal and the output of the second output buffer is determined by the second read enable signal
KR93012135A 1993-06-30 1993-06-30 Dual port ram capable of input/output simultaneously on dual KR960001779B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93012135A KR960001779B1 (en) 1993-06-30 1993-06-30 Dual port ram capable of input/output simultaneously on dual

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93012135A KR960001779B1 (en) 1993-06-30 1993-06-30 Dual port ram capable of input/output simultaneously on dual

Publications (2)

Publication Number Publication Date
KR950001762A KR950001762A (en) 1995-01-03
KR960001779B1 true KR960001779B1 (en) 1996-02-05

Family

ID=19358377

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93012135A KR960001779B1 (en) 1993-06-30 1993-06-30 Dual port ram capable of input/output simultaneously on dual

Country Status (1)

Country Link
KR (1) KR960001779B1 (en)

Also Published As

Publication number Publication date
KR950001762A (en) 1995-01-03

Similar Documents

Publication Publication Date Title
EP0411747A3 (en) Multiple instruction decoder
TW330298B (en) Block write power reduction
WO1996024897A3 (en) Parallel processing redundancy scheme for faster access times and lower die area
NL7207216A (en)
KR960001779B1 (en) Dual port ram capable of input/output simultaneously on dual
TW289824B (en) Semiconductor memory device
KR850700162A (en) Output Comparison Control System and Method for Data Processing Equipment
JPS57182869A (en) Document processing device
DE3765695D1 (en) PROGRAMMABLE CIRCUIT ARRANGEMENT.
KR960009469B1 (en) Transmission controller of master side between buses with different data array
KR920701881A (en) PC signal transmission control method
JPS57106966A (en) Error check system for data transmission bus
SU1631729A1 (en) Binary-to-unitary binary code converter
TW344048B (en) Method for controlling write path of semiconductor memory system with an address transition detector
JPS6473834A (en) Synchronizing system
TW353253B (en) Method for the generation of an output clock signal, which can be used for controlling a data output as a function of one of a plurality of input clock signals
RU1798795C (en) Transputer for uniform computing structure
KR970008788B1 (en) Redundancy circuit using latch circuit
AU6253486A (en) Method and circuit arrangement for the transmission of data signals between control devices connected to one another via a loop system
JPS6486276A (en) Automatic circuit designing system
JPS5717062A (en) Parity checking system
KR970007666A (en) System control signal transmission circuit
JPS6421659A (en) Common bus control system
KR970009969B1 (en) Data output device of semiconductor
TW287254B (en) Memory look-up method and device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19970829

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee