JPS6421659A - Common bus control system - Google Patents

Common bus control system

Info

Publication number
JPS6421659A
JPS6421659A JP17955287A JP17955287A JPS6421659A JP S6421659 A JPS6421659 A JP S6421659A JP 17955287 A JP17955287 A JP 17955287A JP 17955287 A JP17955287 A JP 17955287A JP S6421659 A JPS6421659 A JP S6421659A
Authority
JP
Japan
Prior art keywords
bus occupying
gnt6
gnt0
bus
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17955287A
Other languages
Japanese (ja)
Inventor
Hajime Sato
Shinji Nishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17955287A priority Critical patent/JPS6421659A/en
Publication of JPS6421659A publication Critical patent/JPS6421659A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Abstract

PURPOSE:To prevent plural bus occupying right signals from simultaneouse sending out and to early detect the trouble of a bus occupying connecting circuit by comparing the input of an encoder to be the bus occupying right signal and the output of a decoder, and generating an error signal when a dissident bit is detected. CONSTITUTION:An encoder 41 encodes bus occupying signals GNT0-GNT6 to be inputted based on a matrix, they are decoded in a decoder circuit 42 and bus occupying right signals GNT0'-GNT6' are generated. The bus occupying right signals GNT0-GNT6 from a bus occupying right sending circuit are compared with the bus occupying right signals GNT0'.GNT6', which are the outputs of the decoder 42, in a comparing circuit 43 and when the dissident bit is detected, the error signal is generated.
JP17955287A 1987-07-17 1987-07-17 Common bus control system Pending JPS6421659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17955287A JPS6421659A (en) 1987-07-17 1987-07-17 Common bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17955287A JPS6421659A (en) 1987-07-17 1987-07-17 Common bus control system

Publications (1)

Publication Number Publication Date
JPS6421659A true JPS6421659A (en) 1989-01-25

Family

ID=16067736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17955287A Pending JPS6421659A (en) 1987-07-17 1987-07-17 Common bus control system

Country Status (1)

Country Link
JP (1) JPS6421659A (en)

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