KR950001762A - Dual port RAM capable of input / output simultaneously in both directions - Google Patents

Abstract

The present invention relates to a dual port RAM in which a dual port RAM having two system input / output terminals, in particular, leads / writes at a high speed in both directions at the same time. A first input buffer connected to a data bus, a second input buffer connected to a data bus of an input / output terminal of a second system, and output terminals of the first and second input buffers in common and are outputted from the respective output terminals. A first output buffer connected to an output terminal of the latch unit, for outputting data output from an output terminal of the latch unit to a data bus of an input / output terminal of the first system, and an output of the latch unit; A second output connected to a terminal for outputting data output from an output terminal of the latch section to a data bus of an input / output terminal of the second system; A memory device having a control unit for driving a latch operation of the latch unit by a combination input of a buffer and a predetermined write control signal input from input / output terminals of the first and second systems, respectively, is disclosed. Thus, the memory port is composed of one latch unit and four buffer units, and the dual port RAM outputs a busy signal only when the arbitration circuit inputs the input signals in both directions at the same time and at least the write selection signal is input. By providing the above, there is an advantage in that it is possible to perform a bidirectional simultaneous read operation for the same address that cannot be performed by the conventional method. In addition, the read operation may be performed during the bidirectional simultaneous read / write operation with respect to the same address.

Description

Dual port RAM capable of input / output simultaneously in both directions

Since this is an open matter, no full text was included.

2 is a block diagram showing a schematic configuration of a dual port RAM according to the present invention, and FIG. 3 is a block diagram showing a schematic configuration of a memory device according to the present invention.

Claims (9)

In the dual port RAM, the memory cell is operated by a latch unit driven according to a predetermined control signal and a first lead enable signal connected to an output terminal of the latch unit and input from an input / output terminal of a first system. A first output buffer, a second output buffer connected to an output terminal of the latch unit and operated by a second lead-in enable signal input from an input / output terminal of a second system, and input from the first system and the second system, respectively. Logic means for generating the control signal by a combination of first and second write selection signals, wherein the output operation of the first output buffer is determined by the first read enable signal and the second output buffer The output operation of the dual port RAM, characterized in that determined by the second lead enable signal. 2. The dual port RAM of claim 1, wherein the logic means is a logical multiplication circuit having the first and second write select signals as two inputs. In a dual port RAM, a memory pin includes a first input buffer connected to a data bus of an input / output terminal of a first system, a second input buffer connected to a data bus of an input / output terminal of a second system, and the first and second inputs. A latch unit commonly connected to each output terminal of a buffer to input data outputted from each output terminal, and connected to an output terminal of the latch unit, and connected from an output terminal of the latch unit to a data bus of an input / output terminal of the first system. A first output buffer for outputting the output data, a second output buffer connected to an output terminal of the latch unit and outputting data output from an output terminal of the latch unit to a data bus of an input / output terminal of the second system; A first drive for driving the latch operation of the latch unit by a combination input of write control signals inputted from input / output terminals of a first system and a second system, respectively; Dual-port RAM which is characterized by comprising a. 4. The dual port of claim 3, wherein the first output buffer inputs a first lead enable signal input from the first system and drives an output operation whenever the first lead enable signal is input. lamb. 5. The dual port of claim 4, wherein the second output buffer drives the output operation whenever the second lead enable signal is inputted from the second system and the second lead enable signal is input. lamb. In the dual port RAM, a first read decoder for inputting an address input to an input / output terminal of a first system and decoding the output according to a first control signal and a first read enable signal, and the input / output of the first system. A second write decoder for inputting an address input to the terminal and decoding the output signal according to the first control signal and the first write selection signal; A second read decoder that decodes and outputs a control signal and a second read enable signal, and an address input to an input / output terminal of the second system and inputs the address to the second control signal and the second write select signal. A second write decoder for decoded output according to the first and second addresses and first and second write selection signals inputted from the first system and the second system, An arbitration circuit for outputting a busy signal only when each of the input addresses indicates the same address designation and at least one of the first and second write selection signals is input; and the first and second read decoders And a memory cell for inputting each output signal and each output signal of the first and second write decoders, and inputting and outputting each data input and output from the input and output terminals of the first and second systems by these signals. Dual port RAM, characterized in that. 7. The memory system of claim 6, wherein the memory cell comprises: a first input buffer connected to a data bus of an input / output terminal of the first system, a second input buffer connected to a data bus of an input / output terminal of the second system, and the first input buffer; And a latch unit commonly connected to each output terminal of the second input buffer to input data outputted from the respective output terminals, and connected to an output terminal of the latch unit to the data bus of the input / output terminal of the first system. A first output buffer for outputting data output from a negative output terminal, and a second output connected to an output terminal of the latch unit and outputting data output from the output terminal of the latch unit to a data bus of an input / output terminal of the second system; The latch operation of the latch unit is performed by a combination input of a buffer and a write control signal input from the input / output terminals of the first and second systems, respectively. Dual-port RAM which is characterized by comprising a control unit for the same. 8. The dual port RAM of claim 7, wherein the first control signal and the second control signal are chip select signals input from the first system and the second system, respectively. 9. The dual port RAM of claim 8, wherein the first system is connected to a host and the second system is connected to a DSP. ※ Note: The disclosure is based on the initial application.