KR100301813B1 - A word line drive circuit of semiconductor device - Google Patents

Abstract

PURPOSE: A word line driving circuit of a semiconductor device is provided to reduce a chip area by commonly sharing one controller and one predecoder in many banks. CONSTITUTION: A semiconductor device includes many banks(21). Many word line drivers(22) are connected to each bank, drive each bank, and have a latch function. Row decoder(23) is connected to the word line driver, receives a corresponding predecoding signal, and outputs a word line enable signal. A controller(24) receives a command signal, and generates a reset signal. A predecoder(25) generates a predecoding signal by sampling a row address as a clock signal. A bank state machine(26) receives an address signal corresponding to each bank in case of an active or precharge command, and generates a bank access signal allocated to each bank. Many AND gates receive a predecoding signal of the predecoder and a bank access signal of the bank state machine, perform a logic operation, and output a set signal to the row decoder. NOR gate receives an output signal of the inverter and the reset signal of the controller, performs a logic operation, and outputs a reset signal to the word line driver.

Description

Word line driving circuit of semiconductor device {A WORD LINE DRIVE CIRCUIT OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to word line driving circuits of semiconductor devices, and more particularly, to word line driving circuits of semiconductor devices suitable for reducing chip area.

In general, a word line drive circuit in a semiconductor memory device decodes a row address connected to a memory cell to drive or deactivate a word line connected to the memory cell. .

The spacing of word line wiring becomes tighter as the size of the memory cell decreases, and a semiconductor memory device having a hierarchical word line structure is used to improve such a phenomenon.

Since the hierarchical word line driver circuit has a structure in which a plurality of sub word line drivers are connected to each main word line driver, the spacing between word lines can be reduced.

Hereinafter, a word line driving circuit of a semiconductor device of the prior art will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a word line driver circuit of a semiconductor device of the related art.

As shown in FIG. 1, the word line driver circuit of the semiconductor device of the prior art includes a plurality of banks 11 and a plurality of word line driver units connected to the banks 11 to drive the banks. 12, a plurality of row decoders 13 connected to the respective word line drivers 12 to output row addresses to the word lines, an active signal and a precharge (command) signal; The controller 14 controls and outputs the enable signal XEN and the reset signal CLRxb based on the precharge signal, and receives and samples the clock signal CLK and the row address signal to predecode the signal. It consists of a predecoder section 15 for outputting the.

Here, the control unit 14 outputs the enable signal XEN to the predecoder unit 15 and the low decoder unit 13 when the active signal is input, but the reset signal CLRxb when the precharge signal is input. Is generated to reset the predecoding signal PX output from the predecoder section 15.

In the word line driving circuit of the semiconductor device of the related art, which is configured as described above, each of the banks 11 includes one control unit 14 and one predecoder unit 15, respectively.

In addition, since the word line driver 12 does not have a built-in latch, a corresponding predecoding signal PX must be maintained to maintain the word line.

Subsequently, in the precharge and auto-precharge operation, the reset signal CLRxb of the word line driver 12 is reset by the control unit 14 to reset the predecoder 15 so as to predecode the signal PX. Keeps " Low " to reset the wordless driver 12 without latch.

However, the following problems have been encountered in the word line driving circuit of the semiconductor device of the related art as described above.

In other words, the control area and the predecoder part are respectively configured in the plurality of banks, thereby increasing the chip area.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a word line driving circuit of a semiconductor device which reduces a chip area by sharing a control unit and a predecoder unit in common in a plurality of banks. .

1 is a block diagram illustrating a word line driver circuit of a semiconductor device of the related art.

FIG. 2 is a block diagram illustrating a wonline driving circuit of a semiconductor device according to the present invention. FIG.

3 is a timing diagram of a word line driver circuit of a semiconductor device according to the present invention.

Explanation of symbols for main parts of the drawings

21: bank 22: word line driver

23: low decoder unit 24: control unit

25: predecoder section 26: bank state machine section

27: logic circuit portion 27a: AND gate

27b: inverter 27c: OR gate

The word line driving circuit of a semiconductor device according to the present invention for achieving the above object is a word line driving circuit of a semiconductor device composed of a plurality of banks, is connected to each of the banks to drive the bank and has a latch function A plurality of word line drivers, a low decoder unit connected to the word line driver to receive a corresponding pre-decoding signal and outputting a word line enable signal, and a control to generate a reset signal by receiving command signals A predecoder section for sampling a row address as a clock signal and outputting a predecoding signal, and a bank access signal allocated to each bank in response to an address signal corresponding to each bank inputted during an active or precharge command. A bank state machine unit for generating a predecoding signal and the predecoder unit Receives a plurality of AND gates for receiving the bank access signal of the bank state machine unit and performing a logic operation to output a set signal to the low decoder unit, receiving an output signal of the inverter for inverting the bank access signal of the bank state machine unit, and a reset signal of the controller unit. And a NOR gate for outputting a reset signal to the word line driver by performing a logic operation.

Hereinafter, a word line driving circuit of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a word line driving circuit of a semiconductor device according to the present invention.

As shown in FIG. 2, a plurality of banks 21, a plurality of word line drivers 22 connected to each of the banks 21 to drive the banks, and having a latch function, and the word line drivers ( 22) receives a corresponding predecoding signal and outputs a word line enable signal and a command signal (active signal, precharge signal, auto precharge signal, etc.). The control unit 24 generating the reset signal CLRxb, the low address and the clock signal CLK are sampled and output, and the predecoding signal PX is output. The bank state machine which receives the predecoder section 25 which holds up to the reflash command, and receives the address signal input at the time of an active or precharge command and generates the bank access signal XBANK which is allocated to each bank 21. Bank State M achine).

The word line is set or reset only for the banks in which the respective banks 21 are enabled, and the word circuits of the banks other than the banks 21 maintain the previous state. It is configured to include.

Herein, the configuration and operation of the logic circuit unit 27 will be described in detail.

First, the predecoding signal PX of the predecoder section 25 and the bank access signal XBANK of the bank state machine section 26 are received and logically operated to output the set signal Set to the low decoder section 23. A plurality of AND gates 27a, an output signal of the inverter 27b for inverting the bank access signal of the bank state machine unit 26, and a reset signal CLRxb of the control unit 24 are received and logically operated. It consists of a NOR gate 27c which outputs a reset signal to the line driver 22.

3 is a timing diagram of a word line driver circuit of the semiconductor device according to the present invention.

As shown in FIG. 3, when the active command ACT 0 for operating the bank 0 21 at the timing 1 of the clock signal CLK enters together with the row address R ADD, the predecoder section 25. ) Samples the row address and pre-decodes it and maintains its state.

Subsequently, the bank state machine unit 26 enables XBANK <0>, which is an access signal of the bank 0 21, and the predecoding signal PX accesses the low decoder unit 23 of the bank 0 21. To set the word line of the corresponding address.

At this time, since the word line driver 22 has a latch function, the word line driver 22 maintains the set state.

Subsequently, when the next active command ACTV1 is input at timing 3, the predecoder 25 changes the state of the predecoding signal PX to a result of decoding a new row address and maintains it.

On the other hand, the bank state machine part 26 resets XBANK <0> and sets the XBANK1.

The predecoding signal PX is applied to the row decoder 23 of the bank 1 21 by XBANK <1> to enable the word line corresponding to the bank 1 21.

Subsequently, when the bank 2 21 is input to the precharge command at timing 4, a reset signal CLRXb pulse is generated from the control unit 24, and the bank state machine unit 26 receives XBANK <2>. Enable it.

Then, the reset signal CLRxb is input to the bank 2 21 to reset the word line driver 22 regardless of the decoding of the predecoding signal PX, and the word line driver 22 is reset. Keep state.

When the auto-precharge 0 command is input at the 5th time, the bank state machine unit 26 enables XBANK <0> to access XBANK <0>, and the regeneration generated by the controller 24 is performed. The set signal CLRxb resets the word line of XBANK <0>.

As described above, the word line driving circuit of the semiconductor device according to the present invention has the following effects.

First, by using the bank access control signal and using the latched word line driver, only the word line driver can be reset during precharge, so the output of the predecoder part does not need to be reset every precharge, and thus the predecoding signal. Can reduce power consumption associated with

Second, the chip area can be minimized by using the control unit and the predecoder unit in each block in common.

Claims (4)

In a word line driving circuit of a semiconductor device composed of a plurality of banks, A plurality of word line drivers connected to the respective banks to drive the banks and having a latch function; A low decoder unit connected to the word line driver to receive a corresponding pre-decoding signal and output a word line enable signal; A control unit which receives the command signals as inputs and generates a reset signal; A predecoder section for sampling a row address as a clock signal and outputting a predecoding signal; A bank state machine unit which receives an address signal corresponding to each bank input during an active or precharge command and generates a bank access signal allocated to each bank; A plurality of AND gates which receive the predecoding signal of the predecoder section and the bank access signal of the bank state machine section and perform a logic operation to output a set signal to the low decoder section; And a NOR gate configured to receive the output signal of the inverter for inverting the bank access signal of the bank state machine unit and the reset signal of the controller and to perform a logic operation to output the reset signal to the word line driver. Driving circuit. The method of claim 1, And the predecoder unit maintains the predecode signal until the next command signal and the re-flash command after predecoding. The method of claim 1, And the reset signal of the control unit resets the word line driver regardless of pre-decoding signal. The method of claim 1, And the predecoder unit decodes and stores an address input during an active command or a refresh command.