KR950034634A - How pads are formed - Google Patents

How pads are formed Download PDF

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Publication number
KR950034634A
KR950034634A KR1019940011333A KR19940011333A KR950034634A KR 950034634 A KR950034634 A KR 950034634A KR 1019940011333 A KR1019940011333 A KR 1019940011333A KR 19940011333 A KR19940011333 A KR 19940011333A KR 950034634 A KR950034634 A KR 950034634A
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KR
South Korea
Prior art keywords
etching
film
insulating films
pad
barrier
Prior art date
Application number
KR1019940011333A
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Korean (ko)
Other versions
KR0137619B1 (en
Inventor
맹창호
박재수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940011333A priority Critical patent/KR0137619B1/en
Publication of KR950034634A publication Critical patent/KR950034634A/en
Application granted granted Critical
Publication of KR0137619B1 publication Critical patent/KR0137619B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 금속배선막(1)과 TiN막(2)을 차례로 형성하고 소자 보호용 절연막(3,4)을 형성한 후 패드식각 장벽용 감광막(5)을 패터닝하는 단계, 상기 감광막(5)을 식각장벽으로 하여 절연막(4,3)을 식각하는 단계, 노출된 TiN(2)을 CF4 및 O2가스를 사용한 플라즈마 식각으로 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 패드 형성 방법에 관한 것으로, 패드식각시 잔류 TiN막이 발생하지 않도록 하여 와이어 본딩시의 와이어 접촉을 향상시키는 동시에 리페어회로 부위의 하부절연막의 식각을 방지하여 반도체 소자의 신뢰도 및 수율을 향상시키는 효과가 있다.According to the present invention, the metal wiring film 1 and the TiN film 2 are sequentially formed, the device protection insulating films 3 and 4 are formed, followed by patterning the photoresist film 5 for the pad etching barrier. And etching the insulating films 4 and 3 as an etch barrier, and removing the exposed TiN 2 by plasma etching using CF 4 and O 2 gases. Since the residual TiN film is not generated during the etching, the wire contact during the wire bonding is improved, and the etching of the lower insulating layer in the repair circuit area is prevented, thereby improving the reliability and yield of the semiconductor device.

Description

패드(pad)형성 방법How pads are formed

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1C도는 본 발명에 따른 패드 형성 공정도.1A to 1C are diagrams illustrating a pad forming process according to the present invention.

Claims (3)

패드(pad)형성 방법에 있어서, 금속배선막(1)과 TiN막(2)을 차례로 형성하고 소자 보호용 절연막(3,4)을 형성한 후 패드식각 장벽용 감광막(5)을 패터닝 하는 단계, 상기 감광막(5)을 식각장벽으로 하여 절연막(4,3)을 식각하는 단계, 노출된 TiN막(2)을 CF4 및 O2가스를 사용한 플라즈마 식각으로 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 패드 형성 방법.In the method of forming a pad, the metal wiring film 1 and the TiN film 2 are sequentially formed, the device protection insulating films 3 and 4 are formed, and then the patterning film 5 for the pad etching barrier is patterned. Etching the insulating films 4 and 3 by using the photoresist film 5 as an etch barrier, and removing the exposed TiN film 2 by plasma etching using CF4 and O2 gas. Forming method. 제1항에 있어서, 상기 노출된 TiN막(2) 식각은 200℃ 내지 300℃의 온도범위에서 이루어지는 것을 특징으로 하는 패드 형성 방법.The method of claim 1, wherein the exposed TiN film (2) is etched in a temperature range of 200 ° C. to 300 ° C. 3. 제1항 또는 제2항에 있어서, 상기 감광막(5)을 식각 감광막95)을 식각장벽으로 하여 절연막(4,3)을 식각하는 단계 후 감광막(5)을 제거하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 패드 형성 방법.The method of claim 1 or 2, further comprising removing the photoresist film (5) after the etching of the insulating films (4,3) using the photoresist film (5) as an etching barrier. A pad forming method characterized by the above-mentioned. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940011333A 1994-05-24 1994-05-24 Manufacturing method of semiconductor device KR0137619B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940011333A KR0137619B1 (en) 1994-05-24 1994-05-24 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940011333A KR0137619B1 (en) 1994-05-24 1994-05-24 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950034634A true KR950034634A (en) 1995-12-28
KR0137619B1 KR0137619B1 (en) 1998-06-01

Family

ID=19383700

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940011333A KR0137619B1 (en) 1994-05-24 1994-05-24 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR0137619B1 (en)

Also Published As

Publication number Publication date
KR0137619B1 (en) 1998-06-01

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