KR950025938A - Chip Attachment Method and Structure of Ball Grid Array Package - Google Patents

Chip Attachment Method and Structure of Ball Grid Array Package Download PDF

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Publication number
KR950025938A
KR950025938A KR1019940002982A KR19940002982A KR950025938A KR 950025938 A KR950025938 A KR 950025938A KR 1019940002982 A KR1019940002982 A KR 1019940002982A KR 19940002982 A KR19940002982 A KR 19940002982A KR 950025938 A KR950025938 A KR 950025938A
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South Korea
Prior art keywords
chip
grid array
ball grid
bonding material
array package
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KR1019940002982A
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Korean (ko)
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KR0131392B1 (en
Inventor
허영욱
심일권
프레이만 브루스
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황인길
아남산업 주식회사
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Priority to KR1019940002982A priority Critical patent/KR0131392B1/en
Priority to JP6198341A priority patent/JPH07307411A/en
Publication of KR950025938A publication Critical patent/KR950025938A/en
Application granted granted Critical
Publication of KR0131392B1 publication Critical patent/KR0131392B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

본 발명은 BGA패키지의 칩 부착방법 및 그 구조에 대한 것이다. 종래에는 BGA패키지를 제조함에 있어서, 다이부착용 카파층(6)위에 에폭시접착제(8)를 단순 접착하는 방법에 의해 칩(7)을 부착해 왔기 때문에 고온을 수반하는 제조과정 및 신뢰성 시험과정에서 접합력이 미약한 두 구조물(6) (8)간의 접촉경계지점에 박리층(10)이 생겨 제품의 품질저하를 가져오는 폐단이 있었다.The present invention relates to a chip attaching method of a BGA package and its structure. Conventionally, in manufacturing a BGA package, since the chip 7 has been attached by a simple adhesive method of the epoxy adhesive 8 on the die attaching kappa layer 6, the bonding strength in the manufacturing process and reliability test process involving high temperature At the point of contact between the two fragile structures (6) (8), a peeling layer (10) was formed, resulting in a degradation of the product.

본 발명에서는 종래 BGA패키지의 칩부착 방법이 갖는 제결함을 감안하여 상기 다이부착용 카파층(6)과 에폭시접착제(8)의 사이에 전도성 또는 비전도성의 강력접합물질(11)을 접착 개재시키는 방법에 의해 두 구조물(6) (8)의 접착력을 증가시켜 제조과정 및 시험과정에서 발생할 수 있는 박리현상등의 열변형 문제를 미연에 방지토록 함으로써 제품의 품질신뢰성을 보장할 수 있는 것이다.In the present invention, in view of the defects of the conventional chip attachment method of the BGA package, a method of adhesively interposing a conductive or non-conductive strong bonding material 11 between the die attach kappa layer 6 and the epoxy adhesive (8). By increasing the adhesion of the two structures (6) (8) to prevent thermal deformation problems such as peeling phenomenon that can occur in the manufacturing process and test process in advance can ensure the quality reliability of the product.

Description

볼리그리드어레이(Ball Grid Array) 패키지의 칩 부착방법 및 그 구조Chip Attachment Method and Structure of Ball Grid Array Package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 볼리그리드어레이 패키지의 구조에 있어서 제조과정 및 신뢰성시험을 거치는 동안 고온에 의해 에폭시 접착제와 동판사이에 박리층이 생기는 상태를 예시한 도면.2 is a view illustrating a state in which a peeling layer is formed between the epoxy adhesive and the copper plate due to high temperature during the manufacturing process and the reliability test in the structure of the ball grid array package.

Claims (8)

다이장착용 카파층(6)위에 에폭시접착제(8)을 묻히고 그위에 칩(7)을 붙이는 방법에 의해 볼그리드어레이 패키지를 제조함에 있어서,상기 다이 장착용 카파층(6)위에 강력접합물질(11)을 접착하고 동 접합물질(11)위에 에폭시접착제(8)을 접착하는 방법에 의해 두 구조물(6)(8)간의 접착력이 증가되도록 함을 특징으로 하는 볼그리드어레이 패키지의 칩 부착방법.In manufacturing a ball grid array package by applying an epoxy adhesive 8 on a die mounting kappa layer 6 and attaching a chip 7 thereon, a strong bonding material is formed on the die mounting kappa layer 6. 11) A method of attaching a chip of a ball grid array package, characterized in that the adhesion between the two structures (6) (8) is increased by bonding the epoxy adhesive (8) on the bonding material (11). 제1항에 있어서, 강력접합물질(11)로 에폭시솔더레지스트(Epoxy Solder resist)를 사용함을 특징으로 하는 볼그리드어레이 패키지의 칩 부착방법.The method of claim 1, wherein an epoxy solder resist is used as the strong bonding material (11). 제1항에 있어서, 강력접합물질(11)로 점착테이프를 사용함을 특징으로 하는 볼그리드어레이 패키지의 칩 부착방법.The method of attaching the chip of the ball grid array package according to claim 1, wherein the adhesive tape is used as the strong bonding material. 제1항에 있어서, 강력접합물질(11)로 폴리이미드(Polylimide)를 사용함을 특징으로 하는 볼그리드어레이 패키지의 칩 부착방법.The method of attaching the chip of the ball grid array package according to claim 1, wherein a polyimide is used as the strong bonding material. 제1항에서 4항중 어느 한 항에 있어서, 비전도성 접합물질(11)을 사용할 경우 접합물질(11)에 다수개의 관통공(12)을 천공하여 칩(7)에서 발생하는 열이 PCB보드에 천설되어 있는 방열통로(13)를 통해 외부로 전달되도록 함을 특징으로 하는 볼그리드어레이 패키지의 칩 부착방법.The method according to any one of claims 1 to 4, wherein when using the non-conductive bonding material 11, a plurality of through holes 12 are drilled in the bonding material 11 so that heat generated from the chip 7 is transferred to the PCB board. The method of attaching the chip of the ball grid array package, characterized in that to be transmitted to the outside through the heat dissipation passage (13) installed. 다이부착용 카파층(6)위에 에폭시접착제(8)를 묻히고 그위에 칩(7)을 붙여서 이루어진 볼그리드어레이 패키지 구조에 있어서 상기 다이부착용 카파층(6)과 에폭시접착제(8)사이에 강력접합물질(11)을 접착 게재시킨 볼그리드어레이 패키지의 칩 부착구조.In the ball grid array package structure in which an epoxy adhesive (8) is applied to a die attaching kappa layer (6) and a chip (7) is attached thereto, a strong bonding material between the die attaching kappa layer (6) and the epoxy adhesive (8). The chip attachment structure of the ball grid array package in which (11) is bonded. 제6항에 있어서, 접합물질(11)이 전도성을 갖도록 함을 특징으로 하는 볼그리드어레이 패키지의 칩 부착구조.7. The chip attachment structure of a ball grid array package according to claim 6, wherein the bonding material is made conductive. 제6항에 있어서, 접합물질(11)로 비전도성을 갖도록 함을 특징으로 하는 볼그리드어레이 패키지의 칩 부착구조.7. The chip attachment structure of a ball grid array package according to claim 6, wherein the bonding material is made non-conductive. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940002982A 1994-02-19 1994-02-19 Ball grid array package KR0131392B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019940002982A KR0131392B1 (en) 1994-02-19 1994-02-19 Ball grid array package
JP6198341A JPH07307411A (en) 1994-02-19 1994-08-23 Ball grid array package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940002982A KR0131392B1 (en) 1994-02-19 1994-02-19 Ball grid array package

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KR950025938A true KR950025938A (en) 1995-09-18
KR0131392B1 KR0131392B1 (en) 1998-04-14

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KR (1) KR0131392B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980018591A (en) * 1996-08-13 1998-06-05 이데이 노부유끼 Semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980018591A (en) * 1996-08-13 1998-06-05 이데이 노부유끼 Semiconductor devices

Also Published As

Publication number Publication date
JPH07307411A (en) 1995-11-21
KR0131392B1 (en) 1998-04-14

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