JPH0423836B2 - - Google Patents

Info

Publication number
JPH0423836B2
JPH0423836B2 JP59126787A JP12678784A JPH0423836B2 JP H0423836 B2 JPH0423836 B2 JP H0423836B2 JP 59126787 A JP59126787 A JP 59126787A JP 12678784 A JP12678784 A JP 12678784A JP H0423836 B2 JPH0423836 B2 JP H0423836B2
Authority
JP
Japan
Prior art keywords
lead
layer
film carrier
opening
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59126787A
Other languages
Japanese (ja)
Other versions
JPS616848A (en
Inventor
Manabu Bonshihara
Kazufumi Terachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP12678784A priority Critical patent/JPS616848A/en
Publication of JPS616848A publication Critical patent/JPS616848A/en
Publication of JPH0423836B2 publication Critical patent/JPH0423836B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は配線基板に関し、特に、フイルムキヤ
リヤ半導体装置を実装するに好適な薄型の配線基
板に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a wiring board, and particularly to a thin wiring board suitable for mounting a film carrier semiconductor device.

(従来技術) これまで、キースイツチや、薄型キヤパシタや
抵抗体を実装する端子を有するフイルム状、又は
薄型のプリント配線基板では、開孔部周囲にフイ
ルムキヤリヤ半導体装置を接続する端子を形成し
たものが実用化されておらず、超薄型の電子部品
の実現が困難であつた。又、他の方法の薄型電子
部品としては、フイルムオンフレーム(FOF)
と称する技術開発がなされているが、フイルム上
への半導体チツプの接着からフレームの形成及び
配線の形成等を蒸着やホトレジスト処理やメツキ
処理等で行い、生産工程が複雑で、工業的レベル
での実用化が困難であつた。
(Prior art) Until now, in film-shaped or thin printed wiring boards having terminals for mounting key switches, thin capacitors, and resistors, terminals for connecting film carrier semiconductor devices have been formed around the openings. has not been put into practical use, making it difficult to create ultra-thin electronic components. In addition, as a thin electronic component using other methods, film-on-frame (FOF)
However, the production process is complicated, with processes such as adhering the semiconductor chip onto the film, forming the frame, and forming the wiring using vapor deposition, photoresist processing, plating processing, etc. It was difficult to put it into practical use.

(本発明の目的) 本発明の目的は、薄型プリント配線基板又はフ
イルム状フレキシブル基板で特に両面配線を行つ
た場合に、信頼性の高いフイルムキヤリヤ半導体
装置の実装を可能にするための新構造の配線基板
を提供することにある。
(Object of the present invention) An object of the present invention is to provide a new structure that enables mounting of a highly reliable film carrier semiconductor device, especially when double-sided wiring is performed on a thin printed wiring board or a film-like flexible board. The purpose of this invention is to provide a wiring board for.

(発明の構成) 本発明は、フイルムキヤリヤ半導体装置を実装
する開孔部を有し、前記フイルムキヤリヤ半導体
装置のリードを接続すべき接続端子が、前記開孔
部周囲に設けられている配線基板において、前記
接続端子を有していない基板面の開孔部周囲の接
続領域内に隔離パターン枠層や配線枠層を有し、
前記リードと前記接続端子を接続すべき領域内で
は、配線層及び配線基板材を含めてほぼ一定の厚
さであることを特徴として構成される。
(Structure of the Invention) The present invention has an opening for mounting a film carrier semiconductor device, and a connection terminal to which a lead of the film carrier semiconductor device is to be connected is provided around the opening. The wiring board has an isolation pattern frame layer or a wiring frame layer in a connection area around the opening on the board surface that does not have the connection terminal,
The area where the lead and the connection terminal are to be connected has a substantially constant thickness including the wiring layer and the wiring board material.

(作 用) フイルムキヤリヤ半導体装置をフレキシブル基
板の開孔部周辺端子に接続するには一括熱圧着す
る接続方式が適しているが、フレキシブル基板の
端子部が均一の高さを有していないと、多リード
を有するフイルムキヤリヤ半導体装置の各々に負
荷される荷重や熱が均一にならなくなり、接続不
良を起し信頼性の劣る半導体装置しか得られない
ことになると考えられる。
(Function) In order to connect the film carrier semiconductor device to the terminals around the openings of the flexible substrate, a connection method of thermocompression bonding all at once is suitable, but the terminals of the flexible substrate do not have a uniform height. In this case, it is thought that the load and heat applied to each film carrier semiconductor device having multiple leads will not be uniform, resulting in poor connections and resulting in a semiconductor device with poor reliability.

第13図は、従来の両面フレキシブル配線基板
の上面図で、第14図は第13図のAA′部の断面
図である。図に示すように、貫通開口部2の周辺
に端子リード3が設けられている。該端子リード
3の設けられている他面には配線リード4が設け
られている。この配線リード4は、フイルムキヤ
リヤ半導体を接続する領域5(2点鎖線部)の内
に含まれているので、基板A−A′部の断面では、
第14図に示す如き状態となつている。
FIG. 13 is a top view of a conventional double-sided flexible wiring board, and FIG. 14 is a sectional view of section AA' in FIG. 13. As shown in the figure, terminal leads 3 are provided around the through opening 2 . A wiring lead 4 is provided on the other surface on which the terminal lead 3 is provided. This wiring lead 4 is included in the region 5 (double-dashed line) that connects the film carrier semiconductor, so in the cross section of the substrate A-A',
The state is as shown in FIG.

このような状態の基板1にフイルムキヤリヤリ
ード7を有する半導体装置6を配置すると第15
図のようになる。この状態でA−A′部断面にお
けるギヤングポンデイング状態が第16図、第1
7図に示してある。
When the semiconductor device 6 having the film carrier lead 7 is placed on the substrate 1 in such a state, the 15th
It will look like the figure. In this state, the gear pumping state in the section A-A' is shown in Figure 16 and Figure 1.
It is shown in Figure 7.

第17図に示したように、配線リード4の端部
において、基板1は屈曲し、ヒーター圧力治具9
及びステージ8による接着作用は、一部のリード
7と、リード3にしか効果がない現象を起す。こ
の接続状態の良否をリードの引張りテストにより
評価した結果が第18図に示してある。第18図
から明らかなように正常な強度の40gr以上のもの
と、10gr未満の極めて強度不良のものが現われて
くることが判つた。従つてこのような現象の発生
しない両面配線基板の開発がフイルムキヤリヤ半
導体装置搭載の薄型電子部品の完成には必要であ
ることが判つた。特に基板開孔部の高さの不均一
が関係深いことが判つたので、本発明では前記基
板開孔周囲の高さを均一にして、フイルムキヤリ
ヤリードのフレキシブル基板への接続条件を均一
とし、フイルムキヤリヤリードと、それぞれのリ
ードに対応するフレシキブル基板の電極端子の信
頼性の高い接続を得るようにしたものである。
As shown in FIG. 17, the substrate 1 is bent at the end of the wiring lead 4, and the heater pressure jig 9
The adhesion effect by the stage 8 causes a phenomenon in which it is only effective on some of the leads 7 and the leads 3. The quality of this connection was evaluated by a lead tension test, and the results are shown in FIG. As is clear from FIG. 18, it was found that those with normal strength of 40 gr or more and those with extremely poor strength of less than 10 gr appeared. Therefore, it has been found that it is necessary to develop a double-sided wiring board in which such a phenomenon does not occur in order to complete a thin electronic component mounted on a film carrier semiconductor device. In particular, it has been found that the non-uniformity of the height of the substrate opening is a significant factor, so in the present invention, the height around the substrate opening is made uniform, thereby making the conditions for connecting the film carrier lead to the flexible substrate uniform. , a highly reliable connection between the film carrier lead and the electrode terminal of the flexible substrate corresponding to each lead is obtained.

(実施例) 以下、本考案の実施例について、図面を参照し
て説明する。
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図、第2図は本発明の第1の実施例の上面
図および下面図をそれぞれ示す。本実施例は0.1
mm厚のガラスエポキシ基板にCuリード層を両面
に形成したものである。図において、11は10mm
角の開孔部12を有する0.1mm厚のガラスエポキ
シ基板で、13は約30μm厚のCuリードで300μm
幅でパターン形成されている。20はエポキシ系ソ
ルダーレジスト膜(20′の境界部の外側が該当す
るが図面では取除いた状態を表示した)で、約
20μm厚で前記Cuパターンをカバーしているコー
ト部である。コート部20のない部分はボンデイ
ングリード端子13と電気接触端子部であるが、
これらのリード部はNiとAuメツキが施こされて
いる。特に、第2図の一点鎖線15内はボンデイ
ング領域であり基板厚とリード厚の総厚が殆んど
一定になるように設計することにより安定したボ
ンデイング性を得るようになつている。実際には
基板厚とCu厚、ソルダーレジスト厚を含めて、
各リード13のところで±5μmとなりほぼ均一の
厚さになつている。B−B′部での断面構造が第
3図に示してある。又、第4図にはボンデイング
状態を示す。これからも明らかなように、領域1
5内には、ボンデイング時の均一な荷重の付加に
たして、均一な荷重が各リード13及び17に加
わるようになつている。17はフイルムキヤリヤ
のSnメツキを0.5μm施した35μm厚のDuリードで
ある。13はあらかじめNiメツキ、Auメツキが
それぞれ4μm、0.5μm施こされているので加熱ヒ
ーター1クツシヨンとステージ18とで加圧すれ
ば容易にAu−Sn共晶合金ができて接合される。
各リードが均一な加熱加圧を受けたため、その接
合部の強度は、第5図に示すような分布を示す、
これからも明らかなように20grを割るような低接
合強度の接合はなく、信頼性の高い薄型電子装置
が得られた。
1 and 2 show a top view and a bottom view, respectively, of a first embodiment of the invention. In this example, 0.1
This is a mm-thick glass epoxy substrate with Cu lead layers formed on both sides. In the figure, 11 is 10mm
A 0.1 mm thick glass epoxy substrate with corner openings 12, 13 is a 300 μm thick Cu lead with a thickness of about 30 μm.
Patterned in width. 20 is an epoxy solder resist film (the area outside the boundary of 20' is shown removed in the drawing), and is approximately
This coat part covers the Cu pattern with a thickness of 20 μm. The part without the coat part 20 is the bonding lead terminal 13 and the electrical contact terminal part.
These lead parts are plated with Ni and Au. In particular, the area within the dotted chain line 15 in FIG. 2 is the bonding area, and by designing the total thickness of the substrate thickness and the lead thickness to be almost constant, stable bonding performance can be obtained. Actually, including the substrate thickness, Cu thickness, and solder resist thickness,
Each lead 13 has a thickness of ±5 μm, which is approximately uniform. A cross-sectional structure taken along line B-B' is shown in FIG. Further, FIG. 4 shows the bonding state. As will be clear from this, Area 1
5, a uniform load is applied to each lead 13 and 17 in addition to the uniform load applied during bonding. 17 is a 35 μm thick Du lead with a film carrier Sn plating of 0.5 μm. 13 is pre-plated with Ni plating and Au plating of 4 .mu.m and 0.5 .mu.m, respectively, so that by applying pressure with heating heater 1 and stage 18, an Au-Sn eutectic alloy is easily formed and bonded.
Since each lead was uniformly heated and pressurized, the strength of the joint showed a distribution as shown in Figure 5.
As is clear from this, there was no bond with a bond strength below 20gr, and a highly reliable thin electronic device was obtained.

第6図は本発明の第2の実施例の下面図であ
り、また第7図は第6図のC−C′面の断面図であ
る。第6図、第7図において、21はフレシキブ
ル基板、22は開孔部、23は端子リード、3
1,31′,32,32′は何れも裏面パターンで
あり、貫通孔すなわち開孔部の周辺のボンデイン
グ領域に属する部分内に均一高さと、弾性維持と
均一加熱性を保持するためのCu層マツトである
配線基板パターンである。
FIG. 6 is a bottom view of a second embodiment of the present invention, and FIG. 7 is a sectional view taken along line CC' in FIG. 6 and 7, 21 is a flexible board, 22 is an opening, 23 is a terminal lead, 3
Reference numerals 1, 31', 32, and 32' are all backside patterns, in which a Cu layer is formed to maintain uniform height, elasticity, and uniform heating within the bonding area around the through hole, that is, the opening. This is a matte wiring board pattern.

Cu層マツト31,31′,32,32′は開孔
部周辺の接合リードの設けられている反対面に枠
状に設けられているが、31,31′,32,3
2′は図示のように各辺に分けて設けて設けられ
ている。
The Cu layer mats 31, 31', 32, 32' are provided in the shape of a frame on the opposite side where the joining leads are provided around the opening.
2' are provided separately on each side as shown in the figure.

なお、本実施例に使用したCu層マツトは15μm
〜45μm厚の銅箔を使用し均一に設けた。また第
7図に示す21のフレキシブル基板はガラス繊維
入りのトリアジンシートで板厚は0.15mmである
が、両面のCu層は接着剤を使つて貼り付ける場
合と、それを使用しないで熱圧接を行うものがあ
るが何れも本発明に使用可能である。
Note that the Cu layer mat used in this example has a thickness of 15 μm.
Copper foil with a thickness of ~45 μm was used and provided uniformly. In addition, the flexible substrate No. 21 shown in Figure 7 is a triazine sheet containing glass fibers and has a thickness of 0.15 mm, but the Cu layers on both sides can be attached using adhesive or thermo-pressure welding without using adhesive. There are several methods that can be used, and any of them can be used in the present invention.

本実施例の配線基板はリードと端子を接続すべ
き領域内では、配線層及び配線基板材を含めて、
ほぼ一定厚さであるので第1の実施例と同様均一
な強固な接続が可能である。しかも上記条件を満
足するCu層マツト31,31′,32,32′が
設けられているので、加熱、加圧時の基板温度の
均一化による安定した接合とCu層の塑性変形の
吸収による基板ソリの縮小に対し効果を発揮でき
る。
The wiring board of this example includes the wiring layer and wiring board material in the area where the leads and terminals are to be connected.
Since the thickness is approximately constant, a uniform and strong connection is possible as in the first embodiment. Moreover, since the Cu layer mats 31, 31', 32, and 32' that satisfy the above conditions are provided, stable bonding is achieved by uniformizing the substrate temperature during heating and pressurization, and the substrate is bonded by absorbing plastic deformation of the Cu layer. It can be effective in reducing warping.

第8図は本発明の第3の実施例の下面図であ
る。第8図においては、必要なテストパツドを除
きソルダーレジスト50で被覆するが図面ではソ
ルダーレジストを除いた状態を表示している。第
8図に示す本実施例は第2の実施例の変形で開孔
部42の周辺のボンデイング領域に属する部分内
に均一高さと、弾性維持と、均一加熱性を保持す
るためのCu層マツト43を有している。この場
合のCu層マツト43は完全に枠状に継つて形成
されている点が第2の実施例と異なるのみで第2
の実施例と同様の効果を発揮することが出来る。
FIG. 8 is a bottom view of the third embodiment of the present invention. In FIG. 8, the necessary test pads are covered with a solder resist 50, but the drawing shows the state without the solder resist. The present embodiment shown in FIG. 8 is a modification of the second embodiment, and includes a Cu layer mat in order to maintain a uniform height, maintain elasticity, and maintain uniform heatability within the portion belonging to the bonding area around the opening 42. It has 43. The only difference from the second embodiment is that the Cu layer mat 43 in this case is formed in a complete frame shape.
It is possible to achieve the same effect as in the embodiment.

第9図は本発明の第4の実施例の下面図であ
り、第10図は第9図のD−D′面断面図、第1
1図は第9図のE−E′面断面図である。これらの
図に示す本実施例は第2の実施例の他の変形であ
る。第9図に示すように、開孔部52の周辺のボ
ンデイング領域に属する部分55内に、均一高さ
と、弾性維持と、均一加熱性を保持するための
Cu層マツト62,62′,63,63′が形成さ
れている。これらのCu層マツトは第2,第3の
実施例と異なり部分的にスリツトが形成されてい
る。上記4辺のCu層マツトのうち62,62′の
ものは第10図の断面図に示すように端子リード
53に対応した数だけCu層マツト62′がスリツ
トが形成されてフレキシブル基板51の両面に端
子リードに対象的に形成されCu層マツト62′の
方が端子リード53より幅広に形成されている。
また、他の辺に形成されたCu層マツト63,6
3′は第11図に示すようにCu層マツトにスリツ
トが形成されていることは同じであるがCu層マ
ツト1箇に対し端子リード53は2筒の割合に形
成されている。本実施例に於ても第2,第3の実
施例と同様の効果を発揮することが出来る。なお
第10図、第11図に用いた基板は0.125mm厚の
ポリイミドシートである。
FIG. 9 is a bottom view of the fourth embodiment of the present invention, and FIG. 10 is a sectional view taken along line D-D' in FIG.
FIG. 1 is a sectional view taken along line E-E' in FIG. 9. The present embodiment shown in these figures is another modification of the second embodiment. As shown in FIG. 9, in a portion 55 belonging to the bonding area around the opening 52, a uniform height, elasticity maintenance, and uniform heating property are maintained.
Cu layer mats 62, 62', 63, 63' are formed. Unlike the second and third embodiments, these Cu layer mats are partially formed with slits. Among the Cu layer mats 62 and 62' on the four sides, as shown in the cross-sectional view of FIG. The Cu layer mat 62' is formed symmetrically to the terminal lead and is wider than the terminal lead 53.
In addition, the Cu layer mats 63, 6 formed on the other sides
3' is the same as shown in FIG. 11 except that slits are formed in the Cu layer mat, but two terminal leads 53 are formed for each Cu layer mat. This embodiment can also exhibit the same effects as the second and third embodiments. The substrate used in FIGS. 10 and 11 is a polyimide sheet with a thickness of 0.125 mm.

なお、第2,第3,第4の実施例の配線基板の
端子リードにフイルムキヤリヤ半導体装置のリー
ドをボンデイングし、引張り強度試験を実施した
結果を第12図に示した。図より明らかなように
Cu層マツトが設けられていない第1の実施例の
結果に比較して、加熱、加圧時の基板温度の均一
化による安定した接合とCu層の塑性変形の吸収
による基板ソリの縮小に効果があり、低接合強度
のものは発生しないことが判明した。
The leads of the film carrier semiconductor device were bonded to the terminal leads of the wiring boards of the second, third, and fourth embodiments, and a tensile strength test was conducted. The results are shown in FIG. As is clear from the figure
Compared to the results of the first example in which the Cu layer mat is not provided, it is effective in achieving stable bonding by equalizing the substrate temperature during heating and pressurization, and reducing substrate warpage by absorbing the plastic deformation of the Cu layer. It was found that low bonding strength did not occur.

以上実施例で示したように、フイルムキヤリヤ
半導体装置を実装するフレキシブル基板の接合リ
ード部の基板全体の厚さは出来るだけ均一である
ことが必要であり、これを可能にするには、半導
体装置を配置すべき部分に開孔部を設け、該開孔
部周辺の接合領域内には片面に端子リードを設け
るだけか、あるいは端子リードのない面には枠状
金属マツト層を設ければ良いことが判明した。
As shown in the examples above, it is necessary that the thickness of the entire board of the bonding lead portion of the flexible board on which the film carrier semiconductor device is mounted is as uniform as possible. An opening is provided in the area where the device is to be placed, and a terminal lead is provided on one side in the bonding area around the opening, or a frame-shaped metal mat layer is provided on the surface without the terminal lead. It turned out to be good.

また、この枠状金属マツト層は、Cuに限定さ
れるものでなくAやNiあるいは表面がAuメツ
キ、Agメツキ、Snメツキ、半田メツキ、Niメツ
キ等が施こされていてもよく、またソルダーレジ
ストで均一にカバーされていても良いことは明ら
かである。
Further, this frame-shaped metal mat layer is not limited to Cu, but may be made of A or Ni, or the surface may be plated with Au, Ag, Sn, solder, Ni, etc. It is clear that the resist may be uniformly covered.

また、第6図に示したように、Cuマツト層部
は、ある電気端子やグランド端子あるいはフロー
テイング端子でも良いことは明らかである。
Further, as shown in FIG. 6, it is clear that the Cu mat layer portion may be an electrical terminal, a ground terminal, or a floating terminal.

更に、金属マツト層は片面のみの配線基板に設
けた場合でも効果があることは明らかである。
Furthermore, it is clear that the metal mat layer is effective even when provided on a single-sided wiring board.

(発明の効果) 以上説明したとおり本発明によれば、薄型プリ
ント配線基板又はフイルム状フレキシブル基板で
両面配線を行つた場合に、信頼性の高いフイルム
キヤリヤ半導体装置の実装を可能にできるという
効果が得られる。
(Effects of the Invention) As explained above, according to the present invention, there is an effect that it is possible to mount a highly reliable film carrier semiconductor device when double-sided wiring is performed on a thin printed wiring board or a film-like flexible board. is obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例の上面図、第2
図は第1図の下面図、第3図は第2図のB−B面
断面図、第4図は第1の実施例のボンデイング状
態を示す図、第5図は第1の実施例のボンデイン
グ後のリード引張り強度特性図、第6図、第7図
は本発明の第2の実施例の下面図及びC−C′面断
面図、第8図は本発明の第3の実施例の下面図、
第9図〜第11図は本発明の第4の実施例の下面
図及びD−D′面、E−E′面断面図、第12図は本
発明の第2〜第4の実施例のボンデイング後の引
張り強度特性図、第13図、第14図は従来の配
線基板の上面図及びA−A′面断面図、第15図
は第13図の配線基板にフイルムキヤリヤ半導体
装置を組立てたものの上面図、第16図、第17
図は従来の配線基板へのボンデイング状態を示す
図、第18図は従来の配線基板のボンデイング後
のリードの引張り強度特性図である。 1,11,21,51……フレキシブル基板、
2,12,22,42,52……開孔部、3,1
3,23,53……端子リード、4,14,3
1,31′,32,32′,43,62,62′,
63,63′……裏面パターン、5,15,55
……リード接続領域、6……半導体装置、7,1
7……フイルムキヤリヤ半導体装置のリード、
8,18……ステージ、9,19……ヒーター圧
力治具、10,20,50……ソルダーレジス
ト、33……Cu層マツトのスリツト、20′……
ソルダーレジスト境界部。
FIG. 1 is a top view of the first embodiment of the present invention, and FIG.
The figure is a bottom view of Fig. 1, Fig. 3 is a sectional view taken along line B-B of Fig. 2, Fig. 4 is a view showing the bonding state of the first embodiment, and Fig. 5 is a diagram of the bonding state of the first embodiment. Lead tensile strength characteristics after bonding, FIGS. 6 and 7 are a bottom view and a sectional view taken along line C-C' of the second embodiment of the present invention, and FIG. 8 is a diagram of the third embodiment of the present invention. bottom view,
9 to 11 are bottom views and cross-sectional views along D-D' and E-E' planes of the fourth embodiment of the present invention, and FIG. 12 is a bottom view of the fourth embodiment of the present invention. Figures 13 and 14 show the tensile strength characteristics after bonding. Figures 13 and 14 are top views and cross-sectional views taken along the A-A' plane of conventional wiring boards. Figure 15 shows a film carrier semiconductor device assembled on the wiring board shown in Figure 13. Figures 16 and 17
This figure shows a state of bonding to a conventional wiring board, and FIG. 18 is a diagram showing the tensile strength characteristics of a lead after bonding to a conventional wiring board. 1, 11, 21, 51...flexible board,
2, 12, 22, 42, 52...Opening part, 3, 1
3, 23, 53...terminal lead, 4, 14, 3
1, 31', 32, 32', 43, 62, 62',
63, 63'... Back pattern, 5, 15, 55
...Lead connection area, 6...Semiconductor device, 7,1
7...Lead of film carrier semiconductor equipment,
8, 18... Stage, 9, 19... Heater pressure jig, 10, 20, 50... Solder resist, 33... Cu layer mat slit, 20'...
Solder resist boundary.

Claims (1)

【特許請求の範囲】[Claims] 1 フイルムキヤリヤ半導体装置を実装する開孔
部を有し、前記フイルムキヤリヤ半導体装置のリ
ードを接続すべき接続端子が、前記開孔部周囲に
設けられている配線基板において、前記接続端子
を有していない基板面の開孔部周囲の接続領域内
に隔離パターン枠層や配線枠層を有し、前記リー
ドと前記接続端子を接続すべき領域内では、配線
層及び配線基板材を含めてほぼ一定の厚さである
ことを特徴とする配線基板。
1. In a wiring board having an opening for mounting a film carrier semiconductor device, and a connection terminal to which a lead of the film carrier semiconductor device is to be connected, the connection terminal is provided around the opening. There is an isolation pattern frame layer or a wiring frame layer in the connection area around the opening on the board surface that does not have a A wiring board characterized by having a substantially constant thickness.
JP12678784A 1984-06-20 1984-06-20 Wired substrate Granted JPS616848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12678784A JPS616848A (en) 1984-06-20 1984-06-20 Wired substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12678784A JPS616848A (en) 1984-06-20 1984-06-20 Wired substrate

Publications (2)

Publication Number Publication Date
JPS616848A JPS616848A (en) 1986-01-13
JPH0423836B2 true JPH0423836B2 (en) 1992-04-23

Family

ID=14943924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12678784A Granted JPS616848A (en) 1984-06-20 1984-06-20 Wired substrate

Country Status (1)

Country Link
JP (1) JPS616848A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6157084A (en) * 1995-03-17 2000-12-05 Nitto Denko Corporation Film carrier and semiconductor device using same
JP4383461B2 (en) 2007-03-14 2009-12-16 長野計器株式会社 Sensor and sensor manufacturing method
JP5236377B2 (en) 2008-07-16 2013-07-17 シャープ株式会社 Semiconductor device and display device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5420350B2 (en) * 1975-04-18 1979-07-21

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5420350U (en) * 1977-07-13 1979-02-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5420350B2 (en) * 1975-04-18 1979-07-21

Also Published As

Publication number Publication date
JPS616848A (en) 1986-01-13

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