KR950024424A - Phase Detection Control Circuit - Google Patents

Phase Detection Control Circuit Download PDF

Info

Publication number
KR950024424A
KR950024424A KR1019940000494A KR19940000494A KR950024424A KR 950024424 A KR950024424 A KR 950024424A KR 1019940000494 A KR1019940000494 A KR 1019940000494A KR 19940000494 A KR19940000494 A KR 19940000494A KR 950024424 A KR950024424 A KR 950024424A
Authority
KR
South Korea
Prior art keywords
signal
sync signal
counter
phase detection
flop
Prior art date
Application number
KR1019940000494A
Other languages
Korean (ko)
Other versions
KR960001534B1 (en
Inventor
여정범
Original Assignee
이헌조
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 엘지전자 주식회사 filed Critical 이헌조
Priority to KR1019940000494A priority Critical patent/KR960001534B1/en
Publication of KR950024424A publication Critical patent/KR950024424A/en
Application granted granted Critical
Publication of KR960001534B1 publication Critical patent/KR960001534B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

본 발명은 위상검출제어회로 관한 것으로, LCD모듈의 구동을 위한 클럭발생회로에서 PLL을 사용하여 입력신호와 동기되는 기준클력을 발생시키는 경우 입력신호가 비데오 복합동기신호임에 따라 수직동기신호와 1/2H의 수평동기신호가 존재하여 기준클력 입력신호와 동기시키기가 곤란하던 점을 해결키 위해 디지탈 적으로 복합동기신호에서 수직동기신호와 1/2H의 수평동기신호부분을 검출하여 PLL의 입력신호 동기부에 보내서 선택적으로 입력신호와의 동기비교를 제어함으로써 동기틀어짐을 방지할 수 있게 되므로 화면이 불안정하게 되는 현상을 억제할 수 있게 된 것이다.The present invention relates to a phase detection control circuit. In the case of generating a reference clock synchronized with an input signal using a PLL in a clock generation circuit for driving an LCD module, the input signal is a video synchronous signal and a vertical synchronous signal. In order to solve the difficulty of synchronizing with the reference clock input signal due to the presence of the / 2H horizontal sync signal, the PLL input signal is detected by digitally detecting the vertical sync signal and 1 / 2H horizontal sync signal in the composite sync signal. By sending to the synchronous unit and selectively controlling the synchronous comparison with the input signal, it is possible to prevent the synchronous distortion, thereby suppressing the unstable phenomenon.

Description

위상검출제어회로Phase Detection Control Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 구성도,1 is a block diagram of the present invention,

제2도는 제1도 각부의 출력파형도이다.2 is an output waveform diagram of each part of FIG.

제3도(가)는 종래의 위상검출파형도,3 (a) is a conventional phase detection waveform,

(나)는 본 발명에 따른 위상검출파형도이다.(B) is a phase detection waveform diagram according to the present invention.

Claims (2)

입력되는 매스터 클럭을 분주하여 기준클력을 발생하는 기준클력발생부(10)와, 입력되는 복합동기 신호에서 수평동기신호를 검출하는 수평동기신호 검출부(20)와, 복합동기신호에서 수직동기신호를 검출하는 수직동기신호 검출부(3 0)와, 출력신호에 왜곡이 발생하여 동기가 틀어지는 현상을 방지하기 위해 복합동기신호에서 수직동기신호 이후에 1/2H의 수평동기신호부분을 검출하는 위상검출제어부(40)로 구성됨을 특징으로 하는 위상검출제어회로.The reference clock generator 10 divides the input master clock to generate a reference clock, a horizontal sync signal detector 20 for detecting a horizontal sync signal from the input composite sync signal, and a vertical sync signal from the complex sync signal. A vertical synchronization signal detector 30 for detecting and a phase detection controller for detecting a horizontal synchronization signal portion of 1 / 2H after the vertical synchronization signal in the composite synchronization signal to prevent the synchronization from being distorted due to distortion in the output signal. Phase detection control circuit, characterized in that consisting of (40). 제1항에 있어서, 상기 위상검출제어부(40)는 상기 카운터(32)의 출력단에 프리셋단(PR)이 연결된 D플립플롭(DEF8)과, 15분주용인 카운터(41)와, 상기 카운터(41)의 출력을 반전시키는 인버터(INV10)와, 상기 D플립플롭(DEF7)의 클리어단(CL)에 프리셋단(PR)이 연결되며 수직동기신호가 로우로 되는 순간 하이출력을 내보내는 D플립플롭(DEF9)과, 상기 D플립플롭(DEF9)의 출력후, 상기 카운터(41)를 클리어시키는 인버터(INV11),(INV12)로 구성됨을 특징으로 하는 위상검출제어회로.The counter of claim 1, wherein the phase detection control unit (40) includes a D flip-flop (DEF8) having a preset stage (PR) connected to the output terminal of the counter (32), a counter (41) for 15-minute division, and the counter (41). Inverter INV10 for inverting the output of the power supply, and a D flip-flop that emits a high output when the preset stage PR is connected to the clear stage CL of the D flip-flop DEF7 and the vertical synchronization signal goes low. DEF9) and an inverter (INV11) and (INV12) for clearing the counter (41) after the output of the D flip-flop (DEF9). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940000494A 1994-01-13 1994-01-13 Phase detecting circuit KR960001534B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940000494A KR960001534B1 (en) 1994-01-13 1994-01-13 Phase detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940000494A KR960001534B1 (en) 1994-01-13 1994-01-13 Phase detecting circuit

Publications (2)

Publication Number Publication Date
KR950024424A true KR950024424A (en) 1995-08-21
KR960001534B1 KR960001534B1 (en) 1996-02-01

Family

ID=19375578

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940000494A KR960001534B1 (en) 1994-01-13 1994-01-13 Phase detecting circuit

Country Status (1)

Country Link
KR (1) KR960001534B1 (en)

Also Published As

Publication number Publication date
KR960001534B1 (en) 1996-02-01

Similar Documents

Publication Publication Date Title
KR950035370A (en) Monitor power supply control circuit
JP2001051747A5 (en)
KR920008711A (en) Synchronous signal restoration circuit
KR950024424A (en) Phase Detection Control Circuit
KR950020649A (en) Digital audio signal demodulation device
KR910009048A (en) Image display device circuit including video signal processing circuit and agitator circuit
KR870006771A (en) Synchronization circuit for time magnification signal response
KR970024558A (en) Clock generator
KR0160725B1 (en) Apparatus for synchronizing horizontal synchronous signal
KR930015670A (en) Horizontal Blanking Signal Generator for Multiple Scan Rate Operation
KR950016217A (en) Clock signal generator
JP2968754B2 (en) Clock phase synchronization circuit
KR100341705B1 (en) Method, device, control circuit for power synchronization
JP2623958B2 (en) External synchronization device for TV camera
KR970004640A (en) Sync signal processing circuit of LCD projector
JP3346497B2 (en) Power synchronized pulse generation circuit
KR950022074A (en) Transient elimination circuit and unnecessary switching prevention circuit during redundant clock switching
KR980007543A (en) Horizontal Synchronization Signal Input Compensation Device for Phase-Locked Loop
JPS63129867A (en) Inverter device
KR980006918A (en) 50% Duty Cycle Data Generator (50% Duty Cycle Data Generator)
KR20000055147A (en) Apparatus for Converting Frame Rate of Video Data
KR980007493A (en) Horizontal Synchronization Signal Input Compensation Device for Phase Synchronous Loop
JP2001285262A (en) Phase correction device
KR930023987A (en) TBC's Light Clock Generation Circuit
KR970029283A (en) How to control clamp signal generation

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee