KR950021595A - Capacitor Formation Method of Semiconductor Device - Google Patents

Capacitor Formation Method of Semiconductor Device Download PDF

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Publication number
KR950021595A
KR950021595A KR1019930031922A KR930031922A KR950021595A KR 950021595 A KR950021595 A KR 950021595A KR 1019930031922 A KR1019930031922 A KR 1019930031922A KR 930031922 A KR930031922 A KR 930031922A KR 950021595 A KR950021595 A KR 950021595A
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KR
South Korea
Prior art keywords
forming
film
polysilicon
oxide film
storage electrode
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KR1019930031922A
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Korean (ko)
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KR0122519B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR93031922A priority Critical patent/KR0122519B1/en
Priority to US08/365,344 priority patent/US5536671A/en
Priority to JP6327619A priority patent/JP2620529B2/en
Publication of KR950021595A publication Critical patent/KR950021595A/en
Application granted granted Critical
Publication of KR0122519B1 publication Critical patent/KR0122519B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자의 전하저장전극 형성방법에 관한 것으로 제1폴리실리콘을 비트라인으로 형성하고 비트라인 측벽을 이용하여 전하저장전극을 형성함으로써 표면적을 증대시켜 전하보존전극의 전하보존용량을 극대화시키며 또한 돌출한 비트라인의 전이금속에 의한 실리사이드를 형성함으로써 동작속도를 개선하는 방법에 관한 것이다.The present invention relates to a method of forming a charge storage electrode of a semiconductor device by forming a first polysilicon as a bit line and forming a charge storage electrode using sidewalls of the bit line to maximize the charge storage capacity of the charge storage electrode by increasing the surface area. It also relates to a method of improving the operating speed by forming silicide by the transition metal of the protruding bit line.

Description

반도체 소자의 캐패시터 형성방법Capacitor Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 방법에 의하여 형성된 캐패시터의 단면도2A through 2D are cross-sectional views of capacitors formed by the method of the present invention.

제3A도 내지 제3B도는 본 발명의 다른 실시예를 도시한 단면도.3A to 3B are cross-sectional views showing another embodiment of the present invention.

Claims (3)

반도체 소자의 전하저장전극 형성방법에 있어서, 실리콘기판에 공지의 기술로 트랜지스터를 형성하고 전체 구조 상부에 절연용 산화막, 제1질화막, 평탄화용 산화막을 형성하는 공정과, 평탄화용 산화막, 제1질화막, 절연용 산화막을 사진 식각하여 제1폴리실리콘막을 형성하는 공정과, 제1폴리실리콘막을 패턴하여 비트라인으로 사용하고 평탄화용 산화막을 제거한 후 노출된 제1폴리실리콘막의 표면에 실리사이드를 형성하는 공정과, 열산화막을 형성하고 사진 식각법으로 불순물이온주입 영역의 일부를 노출시키고 전하저장전극으로써 제2폴리실리콘을 적층한 후 비트라인 상부의 소정부분을 제거하고 유전체막과 플레이트 전극을 형성하는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.A method of forming a charge storage electrode of a semiconductor device, comprising: forming a transistor on a silicon substrate by a known technique, and forming an insulating oxide film, a first nitride film, and a planarization oxide film over the entire structure, a planarization oxide film, and a first nitride film Forming a first polysilicon film by photo-etching the insulating oxide film; and forming a first polysilicon film as a bit line by patterning the first polysilicon film, removing a planarization oxide film, and then forming silicide on the exposed surface of the first polysilicon film. And forming a thermal oxide film, exposing a portion of the impurity ion implantation region by photolithography, stacking a second polysilicon as a charge storage electrode, removing a predetermined portion of the upper bit line, and forming a dielectric film and a plate electrode. A method of forming a charge storage electrode of a semiconductor device. 제1항에 있어서, 평탄화용 산화막은 TEO3/O3로 형성되는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.The method of claim 1, wherein the planarization oxide film is formed of TEO 3 / O 3 . 반도체 소자의 전하저장전극 형성방법에 있어서, 실리콘기판에 공지의 기술로 트랜지스터를 형성하고 전체 구조 상부에 절연용 산화막, 제1질화막, 평탄화용 산화막을 형성하는 공정과, 평탄화용 산화막 제1질화막, 절연용 산화막을 사진 식각하여 제1폴리실리콘막을 형성하는 공정과, 제1폴리실리콘막을 패턴하여 비트라인으로 사용하고 평탄화용 산화막을 제거한 후 노출된 제1폴리실리콘막의 표면에 실리사이드를 형성하는 공정과, 전체구조 상부에 제2질화막을 형성하고 사진 식각으로 불순물이 이온 주입 영역일부를 노출시킨 다음 제1전하저장전극용 폴리실리콘을 형성하고 CVD산화막을 형성한 다음 전체구조 상부에 제2전하저장전극용 폴리실리콘을 증착하고 감광막을 도포하는 공정과, 노출된 제2전하저장전극용 폴리실리콘을 식각하고 CVD산화막과 감광막을 제거한 후 유전체막 및 플레이트전극을 형성하는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.A method of forming a charge storage electrode of a semiconductor device, comprising: forming a transistor on a silicon substrate by a known technique, and forming an insulating oxide film, a first nitride film, and a planarization oxide film over the entire structure, a planarization oxide first nitride film, Forming a first polysilicon film by photo-etching the insulating oxide film; forming a first polysilicon film by patterning the first polysilicon film as a bit line, removing the planarization oxide film, and then forming silicide on the exposed surface of the first polysilicon film; Next, a second nitride film is formed on the entire structure, and a portion of the ion implantation region is exposed by photolithography, a polysilicon for the first charge storage electrode is formed, a CVD oxide film is formed, and a second charge storage electrode is formed on the entire structure. A process of depositing polysilicon for coating and applying a photoresist film, etching the exposed second polysilicon for storage electrode, and CVD oxidation Forming a dielectric film and a plate electrode after removing the film and the photosensitive film; ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93031922A 1993-12-28 1993-12-31 Manufacturing method of capacitor of semiconductor device KR0122519B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR93031922A KR0122519B1 (en) 1993-12-31 1993-12-31 Manufacturing method of capacitor of semiconductor device
US08/365,344 US5536671A (en) 1993-12-28 1994-12-28 Method for fabricating capacitor of a semiconductor device
JP6327619A JP2620529B2 (en) 1993-12-28 1994-12-28 Manufacturing method of Dealam capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93031922A KR0122519B1 (en) 1993-12-31 1993-12-31 Manufacturing method of capacitor of semiconductor device

Publications (2)

Publication Number Publication Date
KR950021595A true KR950021595A (en) 1995-07-26
KR0122519B1 KR0122519B1 (en) 1997-11-12

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