KR950020750A - Redundancy Circuit of Semiconductor Device - Google Patents

Redundancy Circuit of Semiconductor Device Download PDF

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Publication number
KR950020750A
KR950020750A KR1019930027766A KR930027766A KR950020750A KR 950020750 A KR950020750 A KR 950020750A KR 1019930027766 A KR1019930027766 A KR 1019930027766A KR 930027766 A KR930027766 A KR 930027766A KR 950020750 A KR950020750 A KR 950020750A
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KR
South Korea
Prior art keywords
node
unit
redundancy circuit
output
circuit
Prior art date
Application number
KR1019930027766A
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Korean (ko)
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KR960008826B1 (en
Inventor
이재진
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR93027766A priority Critical patent/KR960008826B1/en
Publication of KR950020750A publication Critical patent/KR950020750A/en
Application granted granted Critical
Publication of KR960008826B1 publication Critical patent/KR960008826B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

본 발명은 반도체 소자의 리던던시 회로에 관한 것으로, 리던던시 회로에서 리페어할 워드라인 또는 비트라인을 선택하는 어드레스가 입력되는 NMOS형 트랜지스터와 소오스로 해당 리던던시 회로가 리페어 되지 않는 경우에는 접지전압 대신에 전원전압이 인가되도록 하여 어드레스 라인에 연결긴 상기 NMOS형 트랜지스터에서 채널이 형성되지 않도록 함으로써, 어드레스 라인이 구동해야 할 캐패시턴스를 감소시켜 소자의 동작 속도를 향상시키고 전력 소모를 감소시킨 리던던시 회로에 관한 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy circuit of a semiconductor device, wherein an NMOS transistor and a source to which an address for selecting a word line or a bit line to be repaired are input in a redundancy circuit and a source voltage instead of a ground voltage when the corresponding redundancy circuit is not repaired The present invention relates to a redundancy circuit in which an NMOS transistor connected to an address line is applied so that a channel is not formed, thereby reducing capacitance to be driven by the address line, thereby improving the operation speed of the device and reducing power consumption.

Description

반도체 소자의 리던던시 회로Redundancy Circuit of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 리던던시 회로의 실시예를 도시한 회로도.2 is a circuit diagram showing an embodiment of the redundancy circuit of the present invention.

Claims (2)

반도체 소자의 리던던시 회로에 있어서, 리던던시 회로를 프리차지 시키는 프리차지부와, 상기 프리차지부에 접속되며 소자 외부로부터 프로그래밍되는 퓨즈부와, 상기 퓨즈부의 각각의 퓨즈에 접속되며 각각의 게이트로 셀 어레이의 워드라인 또는 비트라인을 선택하는 어드레스 신호가 인가되는 트랜지스터부와, 상기 트랜지스터부의 공통 소오스에 접속되어 리던던시 회로의 리페어 여부에 따라 상기 공통 소오스에 전위가 다른 전압을 각각 인가하는 리페어 감지회로부와, 상기 프리차지부와 퓨즈부가 접속된 노드와 상기 리페어 감지회로부의 출력인 상기 트랜지스터부의 공통 소오스를 입력으로 하여 리던던시 동작 인에이블 신호와 정상 동작 인에이블 신호를 출력하는 신호 출력부를 포함하는 것을 특징으로 하는 리던던시 회로.1. A redundancy circuit of a semiconductor device, comprising: a precharge portion for precharging a redundancy circuit, a fuse portion connected to the precharge portion and programmed from outside of the element, and a respective gate connected to each fuse of the fuse portion; A transistor unit to which an address signal for selecting a word line or a bit line is applied, a repair detecting circuit unit connected to a common source of the transistor unit and applying a voltage having a different potential to the common source depending on whether a redundancy circuit is repaired; And a signal output unit configured to output a redundancy operation enable signal and a normal operation enable signal by inputting a node connected to the precharge unit and the fuse unit and a common source of the transistor unit which is an output of the repair detection circuit unit. Redundancy Circuit. 제1항에 있어서, 상기 리페어 감지회로부는, 전원전압과 제1노드 사이에 접속된 퓨즈와, 상기 제1노드와 접지전압 사이에 접속된 캐패시터와, 상기 제1노드를 입력노드로 하는 제1반전 게이트와, 상기 제1노드와 접지전압 사이에 접속되며 게이트가 상기 제1반전 게이트의 출력노드에 연결된 NMOS형 트랜지스터와, 상기 제1반전 게이트의 출력노드를 입력으로 하고 상기 트랜지스터부의 공통 소오스를 출력으로 하는 제2반전 게이트를 포함하는 것을 특징으로 하는 리던던시 회로.The first circuit of claim 1, wherein the repair detection circuit unit comprises: a fuse connected between a power supply voltage and a first node, a capacitor connected between the first node and a ground voltage, and a first node including the first node as an input node; An NMOS transistor connected between an inverted gate, the first node and the ground voltage, and the gate of which is connected to an output node of the first inverted gate, and an output node of the first inverted gate are inputted, and a common source of the transistor unit is used. A redundancy circuit comprising a second inversion gate as an output. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93027766A 1993-12-15 1993-12-15 Redundancy circuit of semiconductor device KR960008826B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93027766A KR960008826B1 (en) 1993-12-15 1993-12-15 Redundancy circuit of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93027766A KR960008826B1 (en) 1993-12-15 1993-12-15 Redundancy circuit of semiconductor device

Publications (2)

Publication Number Publication Date
KR950020750A true KR950020750A (en) 1995-07-24
KR960008826B1 KR960008826B1 (en) 1996-07-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR93027766A KR960008826B1 (en) 1993-12-15 1993-12-15 Redundancy circuit of semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100510995B1 (en) * 1999-01-09 2005-08-31 주식회사 하이닉스반도체 Repair circuit of semiconductor device
KR100526455B1 (en) * 1999-04-15 2005-11-08 주식회사 하이닉스반도체 Semiconductor device including redundancy enable circuitry

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100510995B1 (en) * 1999-01-09 2005-08-31 주식회사 하이닉스반도체 Repair circuit of semiconductor device
KR100526455B1 (en) * 1999-04-15 2005-11-08 주식회사 하이닉스반도체 Semiconductor device including redundancy enable circuitry

Also Published As

Publication number Publication date
KR960008826B1 (en) 1996-07-05

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