KR950013899B1 - Dram cell manufacturing process - Google Patents
Dram cell manufacturing process Download PDFInfo
- Publication number
- KR950013899B1 KR950013899B1 KR1019920001910A KR920001910A KR950013899B1 KR 950013899 B1 KR950013899 B1 KR 950013899B1 KR 1019920001910 A KR1019920001910 A KR 1019920001910A KR 920001910 A KR920001910 A KR 920001910A KR 950013899 B1 KR950013899 B1 KR 950013899B1
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- forming
- dram cell
- patterning
- capacitor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims 1
- 239000011810 insulating material Substances 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
제 1 도는 종래의 적층형 디램셀의 개패시터를 나타낸 단면도.1 is a cross-sectional view showing a capacitor of a conventional stacked DRAM cell.
제 2 도는 본 발명의 적층형 디램셀의 케패피터를 나타낸 공정 단면도.2 is a cross-sectional view showing a capacitor of a stacked DRAM cell of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P형기판 2 : 산화막1: P-type substrate 2: Oxide film
3 : 제 1 폴리 실리콘 6 , 8 : 포토 레지스트3: first polysilicon 6, 8: photoresist
7 , 9 : 측벽 10 : 절연체7, 9: side wall 10: insulator
11 : 폴리 실리콘11: polysilicon
본 발명은 디램셀(Dynamic Random Access Memory)의 캐패시터(Capacitor)제조방법에 관한 것으로, 특히 캐패시터 노드의 유효 표면적을 확장시켜 좁은 셀로도 대용량 정보를 저장할 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a DRAM (Dynamic Random Access Memory). In particular, the effective surface area of a capacitor node can be extended to store a large amount of information in a narrow cell.
종래의 적층형 디램셀의 캐패시터는 제 1 도와 같이 P형기판(1)상에 산화막(2)을 패터닝(Patterning)하고 이온을 주입하여 n+영역을 형성하며 노드로 사용될 제 1 폴리실리콘(3)을 형성하고 제 1 폴리 실리콘(3)표면에 유전체(4)를 증착시킨후 전표면에 플레이트로 사용될 제 2 폴리 실리콘(5)을 증착하여 이루어졌다.A capacitor of a conventional stacked DRAM cell has a first polysilicon 3 to be used as a node by patterning the oxide film 2 on the P-type substrate 1 and implanting ions to form n + regions as shown in the first diagram. Was formed, and a dielectric 4 was deposited on the surface of the first polysilicon 3, followed by deposition of a second polysilicon 5 to be used as a plate on the entire surface.
그러나 이와같은 종래 기술은 단순히 폴리 실리콘의 두께를 증가시켜 캐패시턴스를 상승시키므로 다음 공정으로 진행될수록 셀 부분과 주변 회로 사이의 간격이 커지기 때문에 공정이 어렵게 되는 결점이 있었다.However, such a prior art simply increases the thickness of the polysilicon to increase the capacitance, so that the process becomes difficult because the gap between the cell portion and the peripheral circuit increases as the next process proceeds.
본 발명은 이와같은 종래의 결점을 감안하여 안출한 것으로 노드의 유효표면적을 확장시켜 좁은 셀 면적에서 큰 캐패시턴스를 갖도록 하여 대용량 정보를 저장할 수 있는 디램셀을 달성하는데 그 목적이 있다.The present invention has been made in view of the above-mentioned drawbacks, and an object thereof is to achieve a DRAM cell capable of storing a large amount of information by expanding the effective surface area of a node to have a large capacitance in a narrow cell area.
이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.
제 2 도는 본 발명의 적층형 디램셀의 캐패시터를 나타낸 공정 단면도로서 a와 같은 P형기판(1)위에 산화막(2)을 패터닝하고 이온을 주입하여 n+영역을 형성한 후 제 1 폴리 실리콘(3)을 패터닝하는 것은 종래와 같다.2 is a cross-sectional view illustrating a capacitor of a stacked DRAM cell according to an embodiment of the present invention. After forming an n + region by patterning an oxide film 2 and implanting ions on a P-type substrate 1 as shown in FIG. ) Is patterned as in the prior art.
또한, b와 같이 제 1 폴리 실리콘(3)위에 포토 레지스트(6)를 형성하고 상기 포토 레지스트(6) 양측에 측벽(질화막)(7)을 RECVD(Plasma Enhanced Chemical Vapour Deposition)법으로 형성한 후c와 같이 제 1 폴리 실리콘(3)위에 측벽(산화막)(9)을 포토레지스트(8)를 이용하여 상기 측벽(7)과 중첩되지 않도록 형성한다. 그리고 d와 같이, 측벽(7) (9)영역을 제외한 제 1 폴리 실리콘(3)을 일전깊이 제거하며e와 같이 상기 측벽(7) (9)을 제거하고 제 1 폴리 실리콘(3) 표면에 절연체(유전체)(10)를 형성한 후 전표면이 도포되도록 플레이트로 사용될 폴리 실리콘(11)을 증착한다.In addition, as shown in FIG. 6, photoresist 6 is formed on the first polysilicon 3, and sidewalls (nitride film) 7 are formed on both sides of the photoresist 6 by RECVD (Plasma Enhanced Chemical Vapor Deposition). As shown in c, a sidewall (oxide film) 9 is formed on the first polysilicon 3 so as not to overlap with the sidewall 7 using the photoresist 8. And as shown in d, the first polysilicon 3, except for the region of the sidewalls 7 and 9, is completely removed, and as shown in e, the sidewalls 7 and 9 are removed and the surface of the first polysilicon 3 is removed. After forming the insulator (dielectric) 10, polysilicon 11 to be used as a plate is deposited so that the entire surface is applied.
이상에서 설명한 바와같이 본 발명은 정밀도가 크게 요구되지 않는 공정으로 노드용 제 1 폴리 실리콘93)의 표면적을 확장시키므로 제한된 셀 영역에서 큰 용량을 얻을 수 있는 효과가 있는 것이다.As described above, the present invention extends the surface area of the first polysilicon 93 for nodes in a process in which precision is not highly demanded, and therefore, a large capacity can be obtained in a limited cell area.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920001910A KR950013899B1 (en) | 1992-02-11 | 1992-02-11 | Dram cell manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920001910A KR950013899B1 (en) | 1992-02-11 | 1992-02-11 | Dram cell manufacturing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930018719A KR930018719A (en) | 1993-09-22 |
| KR950013899B1 true KR950013899B1 (en) | 1995-11-17 |
Family
ID=19328779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920001910A KR950013899B1 (en) | 1992-02-11 | 1992-02-11 | Dram cell manufacturing process |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950013899B1 (en) |
-
1992
- 1992-02-11 KR KR1019920001910A patent/KR950013899B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930018719A (en) | 1993-09-22 |
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