KR950013604B1 - Ic checking device - Google Patents

Abstract

an on/off connecting unit which are turned on/off to select a pin to be detected; a comparing unit which is connected to a pin of an integrated circuit, to compare a voltage to be detected from the pin with an established upper/lower limited voltage; a control signal generating unit for controlling the on/off connection unit; a pattern generating unit for transmitting an output signal to the control signal generating unit to generate a desired control signal; and a result display unit for displaying a connection state of the pin according to the output result of the comparing unit, if the pin is grounded or a disconnection between the pins is generated, when the voltage detected from the pin is deviated from the upper/lower limited voltage.

Description

Pin connection failure detection device of integrated circuit

1 is a circuit diagram of a pin connection failure detection device of an integrated circuit according to the prior art.

2 is a block diagram of a configuration for detecting a pin connection failure in an integrated circuit according to the present invention.

3 is a specific circuit diagram of FIG.

4 is a truth table of the elements constituting FIG.

5 is a timing diagram for each part of FIG.

* Explanation of symbols for main parts of the drawings

11: detection start switch 12, 18: square wave generator

14, 25 to 55: flip-flop 15: buffer

16: counter 17: decoder

19: reset switch 21 to 51: first comparator

22-52: 2nd comparator 23-53: NAND gate

24 to 54: display 111: result display device

113: on / off connection device 115: pattern generator

116: control signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a pin misalignment detection device of an integrated circuit (IC). In particular, the present invention relates to an integrated circuit for detecting an open and short state of an integrated circuit pin in a short time. The present invention relates to a circuit pin connection failure detection device.

Conventional integrated circuit pin connection failure detection device is a voltage measurement window for measuring the voltage as shown in Figure 1, the voltage having a current source (5) at each pin (①, ②, ③, ④, ⑤) of the integrated circuit The measuring device 10 was connected through switches K1, K2, K3, and K4 to detect the state of each pin. For example, a switch between the pin ② and the current source 5 to detect the state of pin ②. Turn on (K1) and turn off the remaining switches (K2, K3, K4) so that a current of several tens of mA in the current source (5) flows from inside the integrated circuit to the voltage measuring device (10). Drive the current source (5) and measure the voltage.

At this time, if the connection of the pins is normal, current flows through the diodes D1-D8 of each pin of the integrated circuit, and a voltage of about 0.7 V is measured, and in the open state such as pin ④ or the ground as pin ⑤ In the case of a short-circuit state with the power supply (GND), a voltage of 0.7 V cannot be measured, and a normal state and a bad state are detected using this.

However, in this method, if pin ② and pin ③ are short-circuited, the result is the same as that of normal state in spite of poor connection of pin. Therefore, short circuit with ground voltage can be detected, but short circuit between pins cannot be detected. have.

In addition, if the number of pins is large, the detection time becomes very long, and the detection efficiency is greatly reduced. In the case of 100 pins, the conventional detection apparatus according to the conventional detection apparatus uses a mechanical relay of the switches K1 to K100 to detect one pin state. It takes about 20ms to turn on / off and takes about 10ms to measure the voltage by driving the voltage measuring device.It takes about 3000ms to detect 100 pins, that is, 3 seconds. When applied to an integrated circuit, there is a problem that the detection efficiency is very low.

Accordingly, an object of the present invention is to solve the above problems and to provide an integrated circuit and a wiring defect device capable of efficiently detecting an open state of a pin or a short circuit state between pins and reducing a detection time.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

In the integrated circuit pin connection failure detection device of the present invention, as shown in FIG. 2, a result display device 111 for displaying a detection result of a pin of an integrated circuit and a voltage value as a result of detecting the plate are set. A comparison device 112 for comparing between the upper and lower reference voltages, an on / off connecting device 113 for selecting a pin to be detected on / off, a clock signal generator 114, and the clock signal generator 114 A pattern generator 115 for generating a pattern in synchronization with a clock signal applied from the signal generator; and a control signal connected to the pattern generator 115 for generating a control signal of the on / off connection device 113. Generator 116.

3 is a detailed circuit diagram of the present invention, assuming that 6 pins on one side of the integrated circuit 1 are connected to the power supply voltage Vcc, the pins are grounded, and the remaining pins ②, ③, ④, and ⑤) are applied with 1.0V, the upper limit reference voltage, on one input terminal to detect the wiring failure status, and the signals transmitted from each pin (②, ③, ④, ⑤) are input to the other input terminal. The lower comparator 0.5V is applied to the first comparators 21, 31, 41, and 51 and the input terminal of one side, and the signal transmitted from the pins (②, ③, ④, ⑤) is input to the other input terminal. The second comparators 22, 32, 42, 52 are connected directly.

NAND gates 23, 33, 43, and 53 are connected to the outputs of the first and second comparators 21 to 51 and 22 to 52, and are connected to the decoder 17 to decode the decoded signal. Switch (S1, S3, S5, S7), which is an on / off connecting device for selecting a pin to be detected accordingly, is connected between the respective pins (2, 3, 4, 5) and the ground voltage. The resistors (R1, R2, R3, R4) are connected between (②, ③, ④, ⑤) and the 5V voltage, and a 5V supply voltage is applied, resulting in poor connection of each pin (②, ③, ④, ⑤). Output inverting terminals of flip-flops 25, 35, 45 and 55 whose status indicators 24 to 54 input the output signals of the respective NAND gates ①, ②, ③, ④ and ⑤. ( )

In addition, the output terminal of the decoder 17 connected to the on / off connection device Is connected to the switch (S2, S4, S6, S8) connected to the clock terminal (CLK) of the flip-flop (25 to 55) through the inverter (I1, I2, I3, I4) to detect the wiring failure of the pin do.

And a clear terminal of each of the flip-flops 25 to 55. The first square wave generator 12 for generating a monostable square pulse is connected when the detection start switch 11 is turned on to start detecting the connection state of the pin, and at the same time, the first square wave generator 12 is disconnected from the first square wave generator 12. When the stable pulse is applied, the flip-flop 14 which outputs a low state until the detection is completed is connected, and the output inverting terminal of the flip-flop 14 ( ) Is connected to a clear terminal of the counter 16 which counts 4 by receiving the clock from the buffer 15 enabled when the output signal is low, and the buffer 15 is connected to the counter 16. A decoder 16 is connected between the switch S1, S3, S5 and S7 to select a switch to detect a wiring failure state of the pins ②, ③, ④ and ⑤ of the integrated circuit according to the output signal. The decoder 17, the first and second spheronization generators 12 and 18 and the first and second comparators 21 to 51, 22 to 52 are shown in FIGS. Operate according to the truth table shown in c).

Referring to the operation of the integrated circuit pin connection failure detection device configured as described above with reference to the timing diagram of FIG. 5, first, the power supply voltage Vcc and the pin ① of the integrated circuit are connected, and the detection start switch 11 is connected. ON to generate the monostable square wave of (c) from the first square wave generator 12.

The square wave resets all of the flip-flops 25, 35, 45, and 55 connected to the square wave generator 12 so as to be connected between the respective flip-flops and the 5V voltage to display the wiring defects. 34, 44, and 54 are all turned off, and are also applied to the flip-flop 14 to invert the output terminal as shown in (b). Makes the output of the low level.

Then, the buffer 13 connected to the flip-flop 14 of (d) is turned on so that an output signal is applied to the input terminals A0 and A1 of the decoder 17 connected to the output terminals Q0 and Q1 of the counter 16, respectively. Accordingly, the decoder 17 decodes and outputs the input signal according to the truth table as shown in the fourth (a) diagram, thereby outputting the output terminal as shown in (f). Is low, the rest is Outputs high as (g), (h), (t), and Turn on switch S1 connected to and turn off switch S2 connected through inverter I1; Switch connected with S3, S5, S7 off, Turn on the switches S4, S6 and S8 connected via inverters I2, I3 and I4.

Therefore, the potential of the input point of the pin (②) of the integrated circuit connected to the switch S1 is maintained at the ground voltage level regardless of the internal state of the integrated circuit, and the output of the second comparator 22 becomes low and the flip-flop 25 The input of goes high.

However, at this time, the switch S2 connected to the clock terminal of the flip-flop 25 is turned off so that the clock signal is not input. Remains high and does not change, so the indicator associated with it is not turned on.

At this time, if any one of the other pins except the pin (2) is open, the input point potential of the pin becomes 5V, and if one of the pins is shorted to the ground voltage, the input point potential of the pin is the ground voltage level. If the pin and the pin are shorted together, the pin input potential of the two pins is the same as the input point potential state regardless of the internal wiring state.

Therefore, if the connection state of the other pins except pin (2) is normal, the input of the flip-flop 25 is low, and the output of the second square wave generator 18 ( The flip-flops The output remains high so the indicator 24 is not on.

However, if either pin is shorted to ground voltage, the flip-flop connected to that pin Since the output goes low and the indicator is turned on and the flip-flop output Q is inverted again and input back to the input of the NAND gate, the corresponding flip-flop has the output Q, Does not change.

That is, when the first clock is input through the buffer 15, the rising state of the clock ( ), The output of counter 16 goes high and decoder 17 outputs Only as low as the rest When high is output and switches S2, S3, S6, and S8 are turned on, the corresponding indicators are turned on or off depending on the wiring status of each pin.

At this time, if the pin ③ and the pin ④ are shorted between pins, the pin ④ becomes the input point potential of the pin ⑤, i.e., the ground voltage level, regardless of opening or shorting of the pin ④ itself. 2 makes the output of the comparator 42 low and a high signal is input to the input terminal D of the flip-flop 45 to make the output of the flip-flop 45 low. Therefore, the indicator 44 is turned on to indicate that the pin ④ is defective.

Subsequently, when the second clock is input through the buffer 15, in the rising state of the clock, the counter 16 becomes high only with the output Q1 and all the remaining output signals are low to output the decoder 17. To make Loru, The low output signal of is connected to only the switches S2, S4, S5, and S8, so that the corresponding indicators are turned on / off according to the connection status of the connected pins.

At this time, if the pin ③ and the pin ④ are shorted between pins, the pin ③ becomes the input point potential of the pin ④, that is, the ground voltage level, regardless of whether the pin ③ is opened or shorted. The second comparator 32 outputs a low, and accordingly high is inputted to the flip-flop 35 to make the output of the flip-flop 35 low.

Accordingly, the indicator 44 is turned on to indicate that the pin ③ is defective.

In addition, when the third clock is input through the buffer 15, in the rising state of the clock, the counter 16 outputs the outputs Q0 and Q1 so that the output of the decoder 17 is high. The output signal of is connected to only the switches S2, S4, S6, and S8, so that the corresponding indicators are turned on / off according to the connection status of the connected pins.

At this time, the pins ③ and 4) are internally shorted as described above, but the input points of the first and second comparators 31, 32, 41, and 42 are high at about 0.7V. .

However, even when the outputs of the first and second comparators 31, 32, 41, and 42 are high as described above, the short circuit between the pins is detected and the marking is turned on, and the result is fed back to the input of the NAND gate 43 so that the flip-flop The output of (35, 45) causes the indicator to remain on.

Subsequently, when the fourth clock is input through the buffer 15, the output Q2 of the counter 16 becomes high and the flip-flop 14 is readset as shown in (j). Since the buffer 15 is disabled, the counter 16 is also cleared, and the connection failure detection process of the integrated circuit pin is terminated.

If a clock of 1 KHz is output from the clock generator 13 in the integrated circuit pin connection failure detection device as described above, 101 clocks are required to detect an integrated circuit having 100 pins, so that 101 × 1 ms (period of 1 KHz clock) Since it is = 101ms, it can be seen that the time used for detecting the same number of pin connection states using a conventional pin connection failure detection device can be saved much more than 3 seconds.

Therefore, according to the present invention, not only the opening of the integrated circuit pin and the short circuit with the ground voltage can be detected, but also the short circuit state between the pin and the pin can be detected, and the defect detection time can be shortened.

Claims (1)

An on / off connection device 113 for selecting a pin to be detected by being turned on / off, a comparator 112 for comparing the voltage detected from the pin with a set upper / lower limit voltage connected to the pin of the integrated circuit; A control signal generator 116 for controlling the on / off connection device 113, a pattern generator 115 for transmitting an output signal to the control signal generator 116 to generate a desired control signal, and the comparison device According to the output result of 112, a pin is grounded or a short circuit occurs between the pins, and the result display device 111 is turned on so that the user can recognize the wiring state of the pin when the voltage detected from the pin is out of the upper and lower limits. Pin connection failure detection device of an integrated circuit, characterized in that.