CN214252507U - Switch fault diagnosis circuit and power supply system - Google Patents
Switch fault diagnosis circuit and power supply system Download PDFInfo
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- CN214252507U CN214252507U CN202022629718.0U CN202022629718U CN214252507U CN 214252507 U CN214252507 U CN 214252507U CN 202022629718 U CN202022629718 U CN 202022629718U CN 214252507 U CN214252507 U CN 214252507U
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Abstract
The utility model discloses a switch failure diagnosis circuit and power supply system. Wherein the circuit comprises a diagnostic module: the diagnostic module includes: the input end of the first sampling unit is connected with the first phase output end of the inverter bridge circuit; the input end of the second sampling unit is connected with the second phase output end of the inverter bridge circuit; the first input end of the DSP processor is connected with the first sampling unit, the second input end of the DSP processor is connected with the second sampling unit, and the DSP processor is used for judging whether the first upper bridge arm switch has a fault according to the first sampling signal output by the first sampling unit; and judging whether the second upper bridge arm switch has a fault according to a second sampling signal output by the second sampling unit. Through the utility model discloses, can accurately judge whether break down to and confirm the power switch's that breaks down position, the follow-up maintenance of being convenient for or change the device.
Description
Technical Field
The utility model relates to an electronic circuit technical field particularly, relates to a switch failure diagnosis circuit and power supply system.
Background
The power switch (a composite full-control voltage-driven power semiconductor device, IGBT, composed of a bipolar triode and an insulated gate field effect transistor) is more and more widely applied to the fields of motor drive, inverters and the like because the driving power of the power switch is small and the saturation voltage is reduced.
As the frequency of use of power switches increases, power switch failure problems frequently result, with the types of failure being most common as open circuit failures and short circuit failures. Fig. 1 is a structural diagram of a conventional inverter bridge circuit, and currently, whether an open-circuit fault or a short-circuit fault occurs is determined by an output current or voltage of an inverter, but since there are a plurality of power switches in an inverter circuit, the conventional method can only determine whether a fault occurs, and cannot accurately determine a fault position.
Aiming at the problem that in the prior art, whether the inverter bridge circuit has a fault or not can only be judged, and the fault position cannot be accurately judged, an effective solution is not provided at present.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides an in provide a switch failure diagnosis circuit and power supply system to can only judge among the solution prior art whether the inverter bridge circuit breaks down, the problem of unable accurate judgement fault location.
In order to solve the technical problem, the utility model also provides a switch failure diagnosis circuit is applied to the inverter bridge circuit, and this switch failure diagnosis circuit includes diagnostic module, diagnostic module includes:
the input end of the first sampling unit is connected with the first phase output end of the inverter bridge circuit and is used for generating a first sampling signal according to the first phase voltage signal and the first pulse signal; the first pulse signal is a driving signal of a first upper bridge arm switch of the inverter bridge circuit;
the input end of the second sampling unit is connected with the second phase output end of the inverter bridge circuit and is used for generating a second sampling signal according to the second phase voltage signal and the second pulse signal; the second pulse signal is a driving signal of a second upper bridge arm switch of the inverter bridge circuit;
the first input end of the DSP processor is connected with the first sampling unit, and the second input end of the DSP processor is connected with the second sampling unit and used for judging whether the first upper bridge arm switch has a fault according to the first sampling signal; and judging whether the second upper bridge arm switch has a fault according to the second sampling signal.
Further, the first sampling unit includes:
and a first exclusive-or gate chip, a first input end of which inputs the first phase voltage signal, a second input end of which inputs the first pulse signal, and which is used for outputting a low-voltage signal when the first phase voltage signal is consistent with the first pulse signal, and outputting a high-voltage signal when the first phase voltage signal is inconsistent with the first pulse signal.
Further, the second sampling unit includes:
and a second exclusive or gate chip, a first input end of which inputs the second phase voltage signal, a second input end of which inputs the second pulse signal, and which is used for outputting a low voltage signal when the second phase voltage signal is consistent with the second pulse signal, and outputting a high voltage signal when the second phase voltage signal is inconsistent with the second pulse signal.
Further, the diagnostic module further comprises:
the input end of the third sampling unit is connected with the first phase output end of the inverter bridge circuit and is used for generating a third sampling signal according to the first phase voltage signal and the third pulse signal; the third pulse signal is a driving signal of a first lower bridge arm switch of the inverter bridge circuit;
the input end of the fourth sampling unit is connected with the second phase output end of the inverter bridge circuit and is used for generating a fourth sampling signal according to the second phase voltage signal and a fourth pulse signal; and the fourth pulse signal is a driving signal of a second lower bridge arm switch of the inverter bridge circuit.
Further, the third sampling unit includes:
the input end of the first inverter is connected with the input first phase voltage signal and is used for inverting the first phase voltage signal to generate a first inverted signal;
and a third exclusive-or gate chip, a first input end of which inputs the first inverted signal and a second input end of which inputs the third pulse signal, for outputting a low level signal when the first inverted signal is consistent with the third pulse signal and outputting a high level signal when the first inverted signal is inconsistent with the third pulse signal.
Further, the fourth sampling unit includes:
the input end of the second phase inverter is connected with an input second-phase voltage signal and is used for inverting the second-phase voltage signal to generate a second inverted signal;
and a fourth exclusive-or gate chip, a first input end of which inputs the second inverted signal and a second input end of which inputs the fourth pulse signal, for outputting a low level signal when the second inverted signal is consistent with the fourth pulse signal and outputting a high level signal when the second phase voltage signal is inconsistent with the second pulse signal.
Further, the fault diagnosis circuit further includes:
the input end of the following module is connected with the positive terminal of the direct current bus of the inverter bridge circuit, and the output end of the following module is connected with the mirror current source module and is used for detecting the change of the voltage of the direct current bus and outputting the voltage which changes along with the voltage of the direct current bus;
and the input end of the mirror current source module is connected with the following module through a first resistor, and the first output end and the second output end of the mirror current source module are respectively connected with the DSP processor and used for outputting the first phase voltage signal and the second phase voltage signal according to the output voltage of the following module.
Further, the following module includes:
the voltage division circuit is formed by connecting a second resistor and a third resistor in series, the first end of the voltage division circuit is connected with the positive terminal of the direct current bus, and the second end of the voltage division circuit is grounded;
and a first input end of the voltage follower is connected between the second resistor and the third resistor, a second input end of the voltage follower is connected with an output end of the voltage follower, and an output end of the voltage follower is connected with the mirror current source module through the first resistor.
Further, the mirror current source module includes:
the first branch circuit comprises a first switch and a fourth resistor, the base electrode and the collector electrode of the first switch are connected with the following module, and the emitter electrode is grounded through the fourth resistor;
the second branch circuit comprises a second switch, a fifth resistor and a sixth resistor, wherein the base of the second switch is connected with the following module, the collector of the second switch is connected with the first-phase output end of the inverter bridge circuit through the fifth resistor, and the emitter of the second switch is grounded through the sixth resistor;
a third branch circuit, which includes a third switch, a seventh resistor and an eighth resistor, wherein the base of the third switch is connected to the following module, the collector is connected to the second phase output terminal of the inverter bridge circuit through the seventh resistor, and the emitter is grounded through the eighth resistor;
a first output end of the mirror current source module is led out between the collector electrode of the second switch and the fifth resistor, and a second output end of the mirror current source module is led out between the collector electrode of the third switch and the seventh resistor.
The utility model also provides a power supply system, including inverter circuit, still include above-mentioned switch failure diagnosis circuit.
Use the technical scheme of the utility model, according to the first looks voltage signal of inverter bridge circuit and the driving signal of the first upper bridge arm switch of inverter bridge circuit generate first sampling signal; generating a second sampling signal according to a second phase voltage signal of the inverter bridge circuit and a driving signal of a second upper bridge arm switch of the inverter bridge circuit; judging whether the first upper bridge arm switch has a fault according to the first sampling signal; and judging whether the second upper bridge arm switch has a fault according to the second sampling signal, accurately judging whether the second upper bridge arm switch has the fault, and determining the position of the power switch with the fault, so that subsequent maintenance or device replacement is facilitated.
Drawings
Fig. 1 is a structural diagram of a conventional inverter bridge circuit;
fig. 2 is a block diagram of a switch fault diagnostic circuit according to an embodiment of the present invention;
fig. 3 is a block diagram of a switch fault diagnostic circuit according to another embodiment of the present invention;
fig. 4 is a block diagram of a fault diagnosis circuit according to another embodiment of the present invention;
fig. 5 is a structural diagram of a follower module and a mirror current source module according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the embodiments of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and "a plurality" typically includes at least two.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, third, etc. may be used to describe the sampling signals in the embodiments of the present invention, the sampling signals should not be limited to these terms. These terms are only used to distinguish between different sampled signals. For example, the first sampling signal may also be referred to as the second sampling signal, and similarly, the second sampling signal may also be referred to as the first sampling signal without departing from the scope of embodiments of the present invention.
The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.
It is also noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in the article or device in which the element is included.
The following describes in detail alternative embodiments of the present invention with reference to the accompanying drawings.
Example 1
This embodiment provides a switch failure diagnosis circuit for realize the switch failure diagnosis method in the above-mentioned embodiment, fig. 2 is according to the utility model discloses a switch failure diagnosis circuit's structure diagram, as shown in fig. 2, includes diagnostic module 1 in this circuit, and diagnostic module 1 specifically includes:
a first sampling unit 11, an input end of which is connected to the first phase output end L of the inverter bridge circuit, and configured to generate a first sampling signal SIG1 according to the first phase voltage signal and the first pulse signal; the first pulse signal is a driving signal of a first upper bridge arm switch of the inverter bridge circuit.
The input end of the second sampling unit 12 is connected to the second phase output end N of the inverter bridge circuit, and is configured to generate a second sampling signal SIG2 according to the second phase voltage signal and the second pulse signal; and the second pulse signal is a driving signal of a second upper bridge arm switch of the inverter bridge circuit.
The first input end of the DSP processor 13 is connected to the first sampling unit, and the second input end of the DSP processor is connected to the second sampling unit, and is configured to determine whether the first upper arm switch fails according to a first sampling signal SIG 1; and judging whether the second upper arm switch has a fault or not according to a second sampling signal SIG 2.
In the switching failure diagnosis apparatus of the present embodiment, the first sampling unit 11 generates the first sampling signal SIG1 from the first phase voltage signal of the inverter bridge circuit and the driving signal of the first upper arm switch of the inverter bridge circuit; generating a second sampling signal SIG2 by a second sampling unit 12 according to the second-phase voltage signal of the inverter bridge circuit and a driving signal of a second upper bridge arm switch of the inverter bridge circuit; judging whether the first upper bridge arm switch has a fault or not according to the first sampling signal SIG1 by the DSP (digital signal processor) 13; and whether the second upper bridge arm switch has a fault is judged according to the second sampling signal SIG2, whether the second upper bridge arm switch has the fault can be accurately judged, the position of the power switch with the fault is determined, and subsequent maintenance or device replacement is facilitated.
Example 2
The present embodiment provides another switch fault diagnosis circuit, fig. 3 is a structural diagram of a switch fault diagnosis circuit according to another embodiment of the present invention, and a corresponding relationship of the first phase voltage signal L _ SIG0 of the on state of the first upper bridge arm switch is: if the first phase voltage signal L _ SIG0 is a high voltage signal, it indicates that the first upper arm switch is on at this time, and accordingly, the first pulse signal PWM1 should be a high voltage signal, and if the first phase voltage signal L _ SIG0 is a low voltage signal, it indicates that the first upper arm switch is off at this time, and accordingly, the first pulse signal PWM1 should be a low voltage signal, that is, if the first upper arm switch has no fault, the first phase voltage signal L _ SIG0 and the first pulse signal PWM1 should be consistent, and if not, it indicates that the fault has occurred, where consistent means that the voltage is the same in high and low conditions, but not the same in value. In order to determine whether the first phase voltage signal is consistent with the first pulse signal and output different sampling signals according to the determination result, as shown in fig. 3, the first sampling unit 11 includes: the first xor gate chip IC1 has a first input terminal to which a first phase voltage signal is input and a second input terminal to which a first pulse signal is input, and the first xor gate chip IC1 outputs a low voltage signal when the first phase voltage signal coincides with the first pulse signal and outputs a high voltage signal when the first phase voltage signal does not coincide with the first pulse signal.
Similarly, the second sampling unit 12 includes: the second xor gate IC2 has a first input terminal to which the second phase voltage signal is input and a second input terminal to which the second pulse signal is input, and outputs a low voltage signal when the second phase voltage signal matches the second pulse signal and outputs a high voltage signal when the second phase voltage signal does not match the second pulse signal.
The DSP processor 13 is specifically configured to: when a first sampling signal SIG1 is at a low level, determining that the first upper arm switch has not failed, and when the first sampling signal SIG1 is at a high level, determining that the first upper arm switch has failed; when second sampling signal SIG2 is at a low level, it is determined that the second upper arm switch has not failed, and when second sampling signal SIG2 is at a high level, it is determined that the second upper arm switch has failed.
After determining that the power switch has failed, it is necessary to specify which type of failure is specific, and therefore, the DSP processor 13 is further configured to: after the first upper bridge arm switch is judged to have a fault, judging the fault type according to the first phase voltage signal and the first pulse signal; and after judging that the second upper bridge arm switch has a fault, judging the fault type according to the second phase voltage signal and the second pulse signal.
Specifically, the DSP processor 13 is specifically configured to: when the first phase voltage signal is a high-voltage signal and the first pulse signal is at a low level, it is indicated that the first upper bridge arm switch is turned off at the moment under normal conditions, but the first upper bridge arm switch is actually turned on at the moment, which indicates that the first upper bridge arm switch is short-circuited, and therefore, the fault type of the first upper bridge arm switch is determined to be a short-circuit fault; when the first phase voltage signal is a low-voltage signal and the first pulse signal is a high level, it indicates that the first upper arm switch should be on at this time under normal conditions, but the first upper arm switch is actually off at this time, it indicates that the first upper arm switch is open, and it is determined that the fault type of the first upper arm switch is an open-circuit fault.
Similarly, when the second phase voltage signal is a high voltage signal and the second pulse signal is a low level, it indicates that under a normal condition, the second upper arm switch should be turned off at this time, but the second upper arm switch is actually turned on at this time, and it is determined that the fault type of the second upper arm switch is a short-circuit fault; when the second phase voltage signal is a low voltage signal and the second pulse signal is a high level, it indicates that the second upper arm switch should be on at this time under normal conditions, but the second upper arm switch is actually off at this time, and it is determined that the fault type of the second upper arm switch is an open-circuit fault.
In the above embodiment, the inverter bridge circuit further includes a first lower bridge arm switch and a second lower bridge arm switch, and in order to implement fault diagnosis of the first lower bridge arm switch and the second lower bridge arm switch, as shown in fig. 4, the diagnosis module 1 further includes:
a third sampling unit 14, an input end of which is connected to the first phase output end L of the inverter bridge circuit, and configured to generate a third sampling signal SIG3 according to the first phase voltage signal and the third pulse signal; the third pulse signal is a driving signal of a first lower bridge arm switch of the inverter bridge circuit;
a fourth sampling unit 15, an input end of which is connected to the second phase output end N of the inverter bridge circuit, and configured to generate a fourth sampling signal SIG4 according to the second phase voltage signal and the fourth pulse signal; and the fourth pulse signal is a driving signal of a second lower bridge arm switch of the inverter bridge circuit.
The corresponding relation of the conducting state first phase voltage signal L _ SIG0 of the first lower bridge arm switch is as follows: if the first phase voltage signal L _ SIG0 is a high voltage signal, it indicates that the first lower arm switch is off at this time, and accordingly, the third pulse signal PWM3 should be a low voltage signal, and if the first phase voltage signal L _ SIG0 is a low voltage signal, it indicates that the first lower arm switch is on at this time, and accordingly, the third pulse signal PWM3 should be a high voltage signal, that is, if the first lower arm switch is not failed, the inverted signal of the first phase voltage signal L _ SIG0 and the third pulse signal PWM3 should be consistent, and if the inverted signal is not consistent, it indicates that the failure occurs, and therefore, the third sampling unit 14 includes:
a first inverter U1, the input end of which is connected to the input first phase voltage signal, for inverting the first phase voltage signal and generating a first inverted signal;
the third xor gate IC3 has a first input terminal to which the first inverted signal is input and a second input terminal to which the third pulse signal is input, and outputs a low level signal when the first inverted signal coincides with the third pulse signal and outputs a high level signal when the first inverted signal does not coincide with the third pulse signal. The DSP processor 13 determines that the first lower arm switch is not in failure when the third sampling signal SIG3 is at a low level, and determines that the first lower arm switch is in failure when the third sampling signal SIG3 is at a high level. After the first lower bridge arm switch is judged to be in fault, judging the fault type according to the first reverse signal and the third pulse signal; specifically, if the first reverse signal is a high-voltage signal and the third pulse signal is a low-voltage signal, which indicates that the first phase voltage signal L _ SIG0 is a low-voltage signal, indicating that the first lower arm switch should be turned off at this time under normal conditions, but the first upper arm switch is actually turned on at this time, it is determined that the fault type of the first lower arm switch is a short-circuit fault; if the first reverse signal is a low-voltage signal and the third pulse signal PWM3 is a high-voltage signal, it indicates that the first phase voltage signal L _ SIG0 is a high-voltage signal, which indicates that the first lower arm switch should be turned on at this time under normal conditions, but the first upper arm switch is actually turned off at this time, and it is determined that the fault type of the first lower arm switch is an open-circuit fault.
Similarly, the on-state second phase voltage signal N _ SIG0 for the second lower leg switch has the corresponding relationship: if the second phase voltage signal N _ SIG0 is a high voltage signal, it indicates that the second lower arm switch is off at this time, and accordingly, the fourth pulse signal PWM4 should be a low voltage signal, and if the second phase voltage signal N _ SIG0 is a low voltage signal, it indicates that the second lower arm switch is on at this time, and accordingly, the fourth pulse signal PWM4 should be a high voltage signal, that is, if the first lower arm switch does not fail, the inverted signal obtained by inverting the second phase voltage signal N _ SIG0 and the fourth pulse signal PWM4 should be identical, and if not identical, it indicates that a failure has occurred. Therefore, the fourth sampling unit 15 includes:
a second inverter U2 having an input terminal connected to an input second phase voltage signal, for inverting the second phase voltage signal to generate a second inverted signal;
the fourth xor gate IC4 has a first input terminal to which the second inverted signal is input and a second input terminal to which the fourth pulse signal is input, and outputs a low level signal when the second inverted signal coincides with the fourth pulse signal and outputs a high level signal when the second phase voltage signal does not coincide with the second pulse signal. The DSP processor 13 determines that the second lower arm switch is not in failure when the fourth sampling signal SIG4 is at a low level, and determines that the second lower arm switch is in failure when the fourth sampling signal SIG4 is at a high level. And after the second lower bridge arm switch is judged to have a fault, judging the fault type according to the specific conditions of the second reverse signal and the fourth pulse signal. Specifically, if the second inverted signal is a high-voltage signal and the fourth pulse signal PWM4 is a low-voltage signal, indicating that the second phase voltage signal N _ SIG0 is a low-voltage signal, which indicates that the second lower arm switch should be turned off at this time under normal conditions, but the second lower arm switch is actually turned on at this time, it is determined that the fault type of the second lower arm switch is a short-circuit fault; if the second inverted signal is a low voltage signal and the fourth pulse signal PWM4 is a high voltage signal, indicating that the second phase voltage signal N _ SIG0 is a high voltage signal, indicating that the second lower arm switch should be turned on at this time under normal conditions, but the second lower arm switch is actually turned off at this time, it is determined that the fault type of the second lower arm switch is an open-circuit fault. By the scheme of the embodiment, the fault diagnosis of all the switches in the inverter bridge circuit is realized.
Fig. 4 is a structural diagram of a fault diagnosis circuit according to another embodiment of the present invention, in which, in specific implementation, since the output voltage of the dc bus may fluctuate, in order to avoid the influence of the output voltage fluctuation of the dc bus on the fault diagnosis result, as shown in fig. 5, the fault diagnosis circuit further includes:
the input end of the following module 2 is connected with a DC bus positive terminal DC + of the inverter bridge circuit, and the output end of the following module is connected with the mirror current source module 3 and used for detecting the change of the DC bus voltage and outputting the voltage which changes along with the DC bus voltage;
the mirror current source module 3 has an input end connected to the follower module 2 through a first resistor R1, and a first output end and a second output end connected to the DSP processor 13, respectively, and is configured to output a first phase voltage signal and a second phase voltage signal according to an output voltage of the follower module 2.
Fig. 5 is a structure diagram of the following module and the mirror current source module according to the embodiment of the present invention, as shown in fig. 5, the following module 2 includes:
the voltage division circuit is formed by connecting a second resistor R2 and a third resistor R3 in series, the first end of the voltage division circuit is connected with the positive terminal DC + of the direct current bus, and the second end of the voltage division circuit is grounded;
the first input end of the voltage follower a is connected between the second resistor R2 and the third resistor R3, the second input end thereof is connected with the output end thereof, and the output end thereof is connected with the mirror current source module 3 through the first resistor R1.
The mirror current source module 3 includes: the first branch circuit comprises a first switch Q1 and a fourth resistor R4, the base electrode and the collector electrode of the first switch Q1 are connected with the follower module 2, and the emitter electrode is grounded through the fourth resistor R4;
the second branch circuit comprises a second switch Q2, a fifth resistor R5 and a sixth resistor R6, the base of the second switch Q2 is connected with the follower module 2, the collector of the second switch Q2 is connected with the first phase output end L of the inverter bridge circuit through the fifth resistor R5, and the emitter of the second switch Q2 is grounded through the sixth resistor R6;
a third branch, wherein a third switch Q3, a seventh resistor R7 and an eighth resistor R8, the base of the third switch Q3 is connected to the follower module 2, the collector is connected to the second phase output terminal N of the inverter bridge circuit through the seventh resistor R7, and the emitter is grounded through the eighth resistor R8; a first output end of the mirror current source module is led out between the collector of the second switch Q2 and the fifth resistor R5, and a second output end of the mirror current source module is led out between the collector of the third switch Q3 and the seventh resistor R7, where the mirror current source module 3 is used to control the first phase voltage signal and the second phase voltage signal to change in the same direction when the output voltage of the dc bus changes, so as to avoid the influence of the output voltage fluctuation of the dc bus on the fault diagnosis result, and improve the accuracy of the fault diagnosis result.
Example 3
The present embodiment provides a switch fault diagnosis circuit, which is applied to an inverter bridge circuit, as shown in fig. 1 mentioned above, DC + is a positive terminal of a DC bus, DC-is a negative terminal of the DC bus, L is a first phase output terminal, and N is a second phase output terminal.
As shown in fig. 4 mentioned above, the switch failure diagnosis circuit further includes the follower module 2 and the mirror current source module 3:
as shown in fig. 5 mentioned above, the input end of the follower module 2 is connected to the positive terminal DC + of the DC bus, the second resistor R2, the third resistor R3 and the voltage follower a constitute a stable voltage source, the terminals L1 and N1 are respectively connected to the first phase output terminal L and the second phase output terminal N, the first switch Q1, the second switch Q2, the third switch Q3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 constitute the mirror current source module 3, the basic parameters of the first switch Q1, the second switch Q2 and the third switch Q3 are the same, and the influence of the bus voltage fluctuation on the test result can be significantly reduced by using the mirror current source.
As shown in fig. 3 mentioned above, the first phase voltage signal L _ SIG0 and the second phase voltage signal N _ SIG0 become the first sampling signal SIG1 and the second sampling signal SIG2 through an exclusive or gate, respectively, and the first phase voltage signal L _ SIG0 and the second phase voltage signal N _ SIG0 also become the third sampling signal SIG3 and the fourth sampling signal SIG4 through an inverter and an exclusive or gate, respectively.
The utility model discloses IGBT fault reason diagnostic circuit's working process as follows:
when the first phase voltage signal L _ SIG0 is a high voltage signal, the inverter U1 outputs a low voltage signal, when the first phase voltage signal L _ SIG0 is a low voltage signal, the inverter U1 outputs a high voltage signal, when the second phase voltage signal N _ SIG0 is a high voltage signal, the inverter U2 outputs a low voltage signal, and when the second phase voltage signal N _ SIG0 is a low voltage signal, the inverter U2 outputs a high voltage signal.
The driving signal voltage of the power switch (IGBT) has a fixed logical relationship with the single-phase voltage signal output by the arm in which it is located, and for the first upper arm switch T1 and the second upper arm switch T2, when the driving signal is a high voltage signal, the corresponding arm output voltage is normally + Vbus and 0V in the open circuit state, and when the driving signal is a low voltage signal, the corresponding arm output voltage is normally 0V and + Vbus in the short circuit state. The first lower arm switch T3 and the second lower arm switch T4 have the opposite logical relationship, and when the driving signal is a high voltage signal, the output voltage of the corresponding arm is normally 0V and + Vbus in the open state, and when the driving signal is a low voltage signal, the output voltage of the corresponding arm is normally + Vbus and 0V in the short state. As shown in fig. 4 mentioned above, the detected single-phase voltage signal output from the ac output terminal is transmitted to the xor gate chip, and logically compared with the driving signal of the corresponding arm switch, the first phase voltage signal L _ SIG0 is compared with the driving signal PWM1 of the first upper arm switch T1, and the inverted signal of the first phase voltage signal L _ SIG0 is compared with the driving signal PWM3 of the first lower arm switch T3; the second phase voltage signal N _ SIG0 is compared with the driving signal PWM2 of the second upper arm switch T2, the inverted signal of the second phase voltage signal N _ SIG0 is compared with the driving signal PWM4 of the second lower arm switch T4, when the feedback signal is not consistent with the driving signal, it indicates that a fault occurs, when the driving signal is a high voltage signal and the actual state of the corresponding arm switch is off, it indicates that an open-circuit fault occurs, and when the driving signal is a low voltage signal and the actual state of the corresponding arm switch is on, it indicates that a short-circuit fault occurs.
Example 4
The embodiment provides a power supply system, which comprises an inverter circuit and a switch fault diagnosis circuit in the above embodiments, and is used for accurately judging whether a fault occurs or not, and determining the position of a power switch with the fault, so as to facilitate maintenance or replacement of devices.
The above-described circuit embodiments are only illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (10)
1. A switch fault diagnosis circuit applied to an inverter bridge circuit, characterized in that the switch fault diagnosis circuit comprises a diagnosis module, and the diagnosis module comprises:
the input end of the first sampling unit is connected with the first phase output end of the inverter bridge circuit and is used for generating a first sampling signal according to the first phase voltage signal and the first pulse signal; the first pulse signal is a driving signal of a first upper bridge arm switch of the inverter bridge circuit;
the input end of the second sampling unit is connected with the second phase output end of the inverter bridge circuit and is used for generating a second sampling signal according to the second phase voltage signal and the second pulse signal; the second pulse signal is a driving signal of a second upper bridge arm switch of the inverter bridge circuit;
the first input end of the DSP processor is connected with the first sampling unit, and the second input end of the DSP processor is connected with the second sampling unit and used for judging whether the first upper bridge arm switch has a fault according to the first sampling signal; and judging whether the second upper bridge arm switch has a fault according to the second sampling signal.
2. The circuit of claim 1, wherein the first sampling unit comprises:
and a first exclusive-or gate chip, a first input end of which inputs the first phase voltage signal, a second input end of which inputs the first pulse signal, and which is used for outputting a low-voltage signal when the first phase voltage signal is consistent with the first pulse signal, and outputting a high-voltage signal when the first phase voltage signal is inconsistent with the first pulse signal.
3. The circuit of claim 1, wherein the second sampling unit comprises:
and a second exclusive or gate chip, a first input end of which inputs the second phase voltage signal, a second input end of which inputs the second pulse signal, and which is used for outputting a low voltage signal when the second phase voltage signal is consistent with the second pulse signal, and outputting a high voltage signal when the second phase voltage signal is inconsistent with the second pulse signal.
4. The circuit of claim 1, wherein the diagnostic module further comprises:
the input end of the third sampling unit is connected with the first phase output end of the inverter bridge circuit and is used for generating a third sampling signal according to the first phase voltage signal and the third pulse signal; the third pulse signal is a driving signal of a first lower bridge arm switch of the inverter bridge circuit;
the input end of the fourth sampling unit is connected with the second phase output end of the inverter bridge circuit and is used for generating a fourth sampling signal according to the second phase voltage signal and a fourth pulse signal; and the fourth pulse signal is a driving signal of a second lower bridge arm switch of the inverter bridge circuit.
5. The circuit of claim 4, wherein the third sampling unit comprises:
the input end of the first inverter is connected with the input first phase voltage signal and is used for inverting the first phase voltage signal to generate a first inverted signal;
and a third exclusive-or gate chip, a first input end of which inputs the first inverted signal and a second input end of which inputs the third pulse signal, for outputting a low level signal when the first inverted signal is consistent with the third pulse signal and outputting a high level signal when the first inverted signal is inconsistent with the third pulse signal.
6. The circuit of claim 4, wherein the fourth sampling unit comprises:
the input end of the second phase inverter is connected with an input second-phase voltage signal and is used for inverting the second-phase voltage signal to generate a second inverted signal;
and a fourth exclusive-or gate chip, a first input end of which inputs the second inverted signal and a second input end of which inputs the fourth pulse signal, for outputting a low level signal when the second inverted signal is consistent with the fourth pulse signal and outputting a high level signal when the second phase voltage signal is inconsistent with the second pulse signal.
7. The circuit of claim 1, wherein the fault diagnosis circuit further comprises:
the input end of the following module is connected with the positive terminal of the direct current bus of the inverter bridge circuit, and the output end of the following module is connected with the mirror current source module and used for detecting the change of the voltage of the direct current bus and outputting the voltage which changes along with the voltage of the direct current bus;
and the input end of the mirror current source module is connected with the following module through a first resistor, and the first output end and the second output end of the mirror current source module are respectively connected with the DSP processor and used for outputting the first phase voltage signal and the second phase voltage signal according to the output voltage of the following module.
8. The circuit of claim 7, wherein the follower module comprises:
the voltage division circuit is formed by connecting a second resistor and a third resistor in series, the first end of the voltage division circuit is connected with the positive terminal of the direct current bus, and the second end of the voltage division circuit is grounded;
and a first input end of the voltage follower is connected between the second resistor and the third resistor, a second input end of the voltage follower is connected with an output end of the voltage follower, and an output end of the voltage follower is connected with the mirror current source module through the first resistor.
9. The circuit of claim 7, wherein the mirror current source module comprises:
the first branch circuit comprises a first switch and a fourth resistor, the base electrode and the collector electrode of the first switch are connected with the following module, and the emitter electrode is grounded through the fourth resistor;
the second branch circuit comprises a second switch, a fifth resistor and a sixth resistor, wherein the base of the second switch is connected with the following module, the collector of the second switch is connected with the first-phase output end of the inverter bridge circuit through the fifth resistor, and the emitter of the second switch is grounded through the sixth resistor;
a third branch circuit, which includes a third switch, a seventh resistor and an eighth resistor, wherein the base of the third switch is connected to the following module, the collector is connected to the second phase output terminal of the inverter bridge circuit through the seventh resistor, and the emitter is grounded through the eighth resistor;
a first output end of the mirror current source module is led out between the collector electrode of the second switch and the fifth resistor, and a second output end of the mirror current source module is led out between the collector electrode of the third switch and the seventh resistor.
10. A power supply system including an inverter circuit, characterized by further comprising the switch failure diagnosis circuit according to any one of claims 1 to 9.
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| CN202022629718.0U CN214252507U (en) | 2020-11-13 | 2020-11-13 | Switch fault diagnosis circuit and power supply system |
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| CN202022629718.0U CN214252507U (en) | 2020-11-13 | 2020-11-13 | Switch fault diagnosis circuit and power supply system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117302341A (en) * | 2023-11-28 | 2023-12-29 | 上海同驭汽车科技有限公司 | Electric power steering system and diagnosis protection method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117302341A (en) * | 2023-11-28 | 2023-12-29 | 上海同驭汽车科技有限公司 | Electric power steering system and diagnosis protection method |
| CN117302341B (en) * | 2023-11-28 | 2024-02-13 | 上海同驭汽车科技有限公司 | Electric power steering system and diagnosis protection method |
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