KR100622071B1 - A measuring method for pin-to-pin defect of IC - Google Patents

Abstract

The present invention relates to a method for measuring pin-to-pin defects using an integrated circuit (IC) test parameter of open / short and leakage current.

In the pin-to-pin defect measuring method of the integrated circuit according to the present invention (a) open / short, to open all the input pins of the integrated circuit (float), apply a current to each pin and measure the voltage (Open / Short, O / S) test step; (b) an inter-pin short test step in which all input pins of the integrated circuit are divided into even and odd pins and tested to model adjacent pins; (c) testing all input pins of the integrated circuit in a low (or high) state and applying 0.0 (or 5.0) [V] to each pin to test input leakage current; And (d) after performing the input leakage current test, applying a 0.0 (or 5.0) [V] to the even pin and the odd pin to measure the current to measure the current between pins by the presence of a leakage resistance between the even and odd pins. Pin leakage current test step of measuring the leakage current; characterized in that it comprises a.

According to the present invention, the test method for the open / short and leakage current, which is an existing test parameter, can be modified to isolate and test the pin-to-pin defects, and to test the pin-to-pin and leakage currents that occupy most of the pin-to-pin defects, thereby making accurate and reliable testing possible. have.

Description

A measuring method for pin-to-pin defect of IC

1A and 1B illustrate test modeling and test methods of an open / short (O / S) which is an IC test parameter.

2A and 2B show a circuit modeling an input leakage current which is an integrated circuit (IC) test parameter.

3A and 3B illustrate an input leakage current test method which is an integrated circuit (IC) test parameter.

4A and 4B show pin-to-pin short circuit modeling for explaining the open / short test according to the present invention.

Figure 5 illustrates an inter-pin open / short test method according to the present invention.

6A and 6B show leakage resistance circuit modeling for explaining the leakage current test according to the present invention.

7A and 7B illustrate a pin-to-pin leakage test (IILpp / IIHpp test) method according to the present invention.

8 illustrates a test sequence of pin-to-pin test parameters for measuring pin-to-pin defects of an integrated circuit according to the present invention.

The present invention relates to a method for testing pin-to-pin defects in an integrated circuit, and more particularly to a method for measuring pin-to-pin defects in an integrated circuit using integrated circuit (IC) parameters such as open / short and leakage current.

In general, the test parameters of an integrated circuit (IC) include open / short (O / S) and leakage current tests.

The DC parameter test is a steady state test. In practice, the DC parameters are the resistance values provided by the silicon. The resistance value changes from a fully shorted (conducted) state, a half shorted state, or a fully open (isolated) state, depending on the operating state of the IC. Therefore, Ohm's law is used to calculate the resistance value for each DC parameter to be measured. All DC parameter values are measured with an Automatic Test Equipment (ATE) with a Parametric Measuring Unit (PMU). The PMU can apply a programmed voltage (current) and measure current (voltage) and measure parameters most accurately. The PMU also has two programmable limiters that compare the measured voltage and current values, and a clamp that limits the measured values.

The purpose of a typical open / short (O / S) test is to check the contact between the interface and the device under test (DUT) and the internal open or short of the IC.

Open / short (O / S) testing is based on the voltage drop across the protection diodes on the input and output pins of the integrated circuit (IC). Protection diodes designed on the pin protect the circuit by forward biasing to abnormal voltage values greater than VDD or less than VSS.

1A and 1B illustrate test modeling and test methods of an open / short (O / S) integrated circuit (IC) test parameter. FIG. 1A is a VDD diode modeling and test method, and FIG. 1B is a VSS diode modeling method. Indicates a test method.

Put all pins low. Measure the diode turn-on voltage by applying +100 (-100) [mA] current to the protection diode D1 (D2) of the pin using a parameter measuring instrument (PMU). If the turn-on voltage is between +0.1 and +1.0 (-1.0) [V], the measured value of the parameter measuring instrument (PMU) is normally short-circuited. If the turn-on voltage is higher than +1.0 (-1.0) [V], the pin If the diode is open or shorted, it is indicated by the clamp value of the PMU.

In addition, the normal input leakage test method first sets all the input pins of the IC to the opposite state to be measured. Then, the worst-case voltage state (VDD for VIH; VSS for VIL) is applied to each input pin and measured or compared for a measurement limit.

2A and 2B show a circuit modeling an input leakage current which is an integrated circuit (IC) test parameter. FIG. 2A shows an integrated circuit (IC) input circuit and FIG. 2B shows an equivalent resistance circuit.

The worst-case current flowing through each input pin is called input leakage and refers to the current IIL (or IIH) flowing through the resistance between the input pin and VDD (or VSS).

3A and 3B illustrate an input leakage current test method, which is an IC test parameter, FIG. 3A illustrates an input leakage current IIL test method, and FIG. 3B illustrates an input leakage current IIH test method.

To measure the IIL or IIH current, all input pins are pulled high for IIL and all input pins are low for IIH. Apply 0.0 [V] for each input pin for IIL and 5.0 [V] for IIH and measure IIL or IIH for the input leakage current applied to the leakage resistance. The input leakage current specification of CMOS ICs usually determines good quality when it is within ± 1 [kW], and when it is out, it makes a bad quality.

The technical problem to be solved by the present invention is to correct the open / short and the input leakage current test, which is an integrated circuit (IC) test parameter, and to measure the pin-to-pin defect of the integrated circuit by adding the pin-to-pin short circuit and the pin-to-pin leakage current test. To provide a way.

In order to solve the above technical problem, the pin-to-pin defect measuring method of an integrated circuit according to the present invention is a method for measuring pin-to-pin defect using an open / short and leakage current, which is an IC test parameter. (a) an open / short test step of floating all input pins of the integrated circuit, applying current to each pin and measuring voltage; (b) an inter-pin short test step in which all input pins of the integrated circuit are divided into even and odd pins and tested to model adjacent pins; (c) bring all input pins of the integrated circuit low and apply 0.0 [V] to each pin, or make all input pins of the integrated circuit high and set 5.0 [V] to each pin. An input leakage current test step of testing an input leakage current by applying]; And (d) after performing the input leakage current test, when 0.0 [V] is applied in step (c), 0.0 [V] is applied to even and odd pins, and 5.0 [v] in step (c). If V] is applied to the pin and the odd pin pin 5.0 leakage current test step to measure the current by measuring the current by the presence of the leakage pin between the even pin and odd pin by the presence of leakage resistance; It is characterized by including.
In addition, the step (b) comprises the steps of (b1) dividing the pins of the integrated circuit into even and odd pins in order to model the adjacent pins; (b2) opening a test equipment (PMU) connected to any one of the odd pins and even pins separated in step (b1) and applying 0 [V] through pin electronics (PE); (b3) opening the pin electronics (PE) and connecting the test equipment (PMU) to even or odd pins to which no voltage is applied through pin electronics in step (b2); And (b4) applying 0.0 [k] to the pin connected to the test equipment in step (b3) using the test equipment (PMU) and measuring a voltage.
In the step (b4), if the even and odd pins are short-circuited, the 0 [V] voltage applied in the step (b2) is measured to determine a short circuit failure. 3) The clamp voltage is measured at 3 [V] to determine good quality.
In addition, the step (d) comprises the steps of (d1) dividing the pins of the integrated circuit into even pins and odd pins to model the adjacent pins; (d2) Open the test equipment (PMU) connected to any one of the odd and even pins identified in step (d) and apply 5.0 [V] to each pin (or each pin) through pin electronics (PE). Applying 0.0 [V] to (d3) if 5.0 [V] is applied in step (d2) to an even or odd pin that is not applied through pin electronics in step (d2); When 0.0 [V] is applied using the equipment PMU and 0.0 [V] is applied in the step (d2), 5.0 [V] is applied using the test equipment PMU to measure the leakage current. Characterized in that it comprises a.
Also, in the step (d3), if there is a leakage resistance between the even and odd pins, the pin-to-pin leakage current IILpp is measured when 0.0 [V] is applied and the pin-to-pin leakage current IIHpp is measured when 5.0 [V] is applied. If there is no leakage resistance, IILpp or IIHpp is 0 [A] because it is open between pins.

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Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4A and 4B show pin-to-pin short circuit modeling for explaining the open / short test according to the present invention. FIG. 4A shows pin-to-pin short circuit modeling and FIG. 4B shows the pin-to-pin short circuit equivalent circuit.

Since even and odd pins are short-circuited, when the D1 and D2 diodes are open, odd-numbered D3 and D4 diodes replace D1 and D2. If the D1 and D2 diodes are short-circuited in the pin-to-pin short circuit, the even and odd pins are in the state of the power supply unit (VDD, VSS), that is, 0 [V]. Therefore, a test method for determining which pin is defective is necessary. In other words, it is necessary to be able to test the short-circuit defect between pins to improve the reliability of the product by identifying and analyzing the exact defect type of the product.

The open / short test according to the invention floats all input pins, applies current to each pin and measures the voltage. Since adjacent pins are floating, the effect of shorting between pins is eliminated.

Figure 5 illustrates an inter-pin open / short test method according to the present invention.

To model the pins as adjacent pins, separate them into even and odd pins. On any of the odd and even pins, for example, open the parameter measuring instrument (PMU) connected to the odd pin and apply 0 [V] through pin electronics (PE), the even pin opens the PE and the parameter measurement Connect the PMU.

Then, using the parameter measuring equipment (PMU) to apply 0.0 [㎂] to the even (odd) pin and measure the voltage. If the even and odd pins are short-circuited, the 0 [V] voltage applied to the odd pins in the above example is measured and determined to be a short circuit failure. If both pins are open, the PMU clamp voltage 3 [V] is measured and judged good.

6A and 6B illustrate leakage resistance circuit modeling for explaining the leakage current test according to the present invention. FIG. 6A illustrates the pin-to-pin leakage resistance modeling and FIG. 6B illustrates the pin-to-pin leakage equivalent resistance circuit.

The input leakage current test measures the leakage current flowing between the input pin and the power supply (VDD / GND). If leakage resistance exists between the adjacent pins and the pins as shown in FIGS. 6A and 6B, the accurate leakage current test may not be performed.

If the IIL current of the even pin is measured according to the leakage current test condition, the even pin is LOW (VSS) state and the odd pin is HIGH (VDD) state, which is modeled as an equivalent resistance circuit as shown in FIG. 6B. In the circuit, R3 goes to VDD and HIGH at both ends, and R2 goes to VSS and LOW at both ends, so it is open.

If the IHH current of the even pin is measured, the even pin becomes HIGH (VDD) and the odd pin is LOW (VSS), which can be modeled as an equivalent resistance circuit as shown in FIG. 6B. In the circuit, R1 becomes VDD and HIGH at both ends, and R4 is open at both ends of VSS and LOW. Due to the pin-to-pin leakage resistance (RPP), the leakage current increases by the pin-to-pin leakage current.

When measuring input leakage current, IIL measures all input pins as HIGH and only pins to be measured as LOW, so the leakage current between adjacent pins (IILpp) is also added at the same time. Since IIH measures all input pins as LOW and only pins to be measured as HIGH, the leakage current between adjacent pins (IIHPP) is added at the same time.

Therefore, the leakage current is expressed as the sum of the input leakage current (IIL / IIH) and the pin-to-pin leakage current (IILPP / IIHPP), so it is impossible to accurately determine the effect of the leakage current. New test algorithms are needed to distinguish between input leakage and pin-to-pin leakage currents.

The present invention proposes a test algorithm for distinguishing the input leakage current from the pin leakage current. The input leakage current is divided into a modified input leakage test (IIL / IIH test) and a pin-to-pin leakage test (IILpp / IIHpp test) to remove the leakage current between pins.

The input leakage current test (IIL / IIH test) forces all input pins to a low state (for IIL) or all input pins to a high state (for IIH), and 0.0 [V] to each pin for a LOW state. In the HIGH state, apply 5.0 [V] to each pin and measure the input leakage current IIL or IIH. Since the adjacent pins are in the LOW or HIGH state, both ends of the leakage resistance between the pins become LOW or HIGH so that the leakage current between the pins IILpp or IIHpp becomes O [A]. Therefore, only pure input leakage current (IIL / IIH) with the pin-to-pin leakage current removed is measured.

The pin-to-pin leakage current test (IILpp / IIHpp) is performed after the input leakage current test. If the input leakage current test passes, only the pin-to-pin leakage current for the pin-to-pin leakage resistance is considered.

Table 1 shows the DC parameter characteristics for leakage current. In the present invention, the pin-to-pin leakage current specification is defined as ± 0.1 [uA] when 10% of the input leakage current value is defined as the pin-to-pin leakage current value based on the VLSI IC of the CMOS process. Since the pin-to-pin leakage current parameters have been defined, an inter-pin leakage current test to measure them is required.

Test parameters Symbol Test method  Remarks Pin name Condition Value Unit Min. Typ. Max. Input leakage current IIL / IIH Input pin VDD = 5V, Vin = 0V - - +1 ㎂ existing VSS = 0V, Vin = 5V -One - - Pin-to-pin leakage current IILpp / IIHpp Input pin Vin = 0V (even pin), Vin = 5V (odd pin) - - +0.1 ㎂ newly open Vin = 0V (odd pins), Vin = 5V (even pins) -0.1 - -

 7A and 7B illustrate a pin-to-pin leakage test (IILpp / IIHpp test) method according to the present invention. FIG. 7A shows an IILpp test and FIG. 7B shows an IIHpp test.

As shown in FIG. 7A, a parameter measuring instrument (PMU) connected to even and odd pins is opened and 5.0 [V] is applied to each plate through PE. If you connect the PMU to any of the even and odd pins, for example the even pin, the PE is automatically disconnected. Using a PMU, apply 0.0 [V] to even pins and measure the current.

If there is a leakage resistance between even and odd pins, the pin-to-pin leakage current IILpp is measured. If there is no leakage resistance, IILpp is measured as 0 [A] since the pin is open.
On the contrary, as shown in FIG. 7B, the PMU connected to the even and odd pins is opened and 0.0 [V] is applied to each pin through the PE. If you connect the PMU to any of the even and odd pins, for example the even pin, the PE is automatically disconnected. Use a parametric measuring instrument (PMU) to apply 5.0 [V] to even pins and measure current.
As shown in FIG. 7A, if a leakage resistance exists between even and odd pins, the pin-to-pin leakage current IIHpp is measured. If there is no leakage resistance, IIHpp is 0 [A] since the pin is open.

8 illustrates a test sequence of pin-to-pin test parameters for measuring pin-to-pin defects of an integrated circuit according to the present invention.

Parameters such as open / short (O / S) secured by the present invention, input leakage and pin to pin short added by the present invention, pin to pin leakage, etc. Measure the pin-to-pin defect of the integrated circuit using

The test order of the parameters may vary depending on the characteristics of the integrated circuit (IC) and the type of failure of the parameters in production.

As described above, the present invention has been described with reference to the embodiments illustrated in the drawings, which are merely exemplary, and it should be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention, the test method for the open / short and leakage current, which is an existing test parameter, can be modified to isolate and test the pin-to-pin defects, and to test the pin-to-pin and leakage currents that occupy most of the pin-to-pin defects, thereby making accurate and reliable testing possible. have.

Claims (5)

In the method of measuring the pin to pin defects using the integrated circuit (IC) test parameters such as open / short and leakage current, (a) an open / short test step of floating all input pins of the integrated circuit, applying current to each pin and measuring voltage; (b) an inter-pin short test step in which all input pins of the integrated circuit are divided into even and odd pins and tested to model adjacent pins; (c) bring all input pins of the integrated circuit low and apply 0.0 [V] to each pin, or make all input pins of the integrated circuit high and set 5.0 [V] to each pin. An input leakage current test step of testing an input leakage current by applying]; And (d) After performing the input leakage current test, when 0.0 [V] is applied in step (c), 0.0 [V] is applied to even and odd pins, and 5.0 [V] in step (c). ] Is applied to the even pin and odd pin 5.0 [V] is applied to measure the current pin-to-pin leakage current test step to measure the leakage current between pins by the presence of leakage resistance between the even pin and odd pin; The pin-to-pin defect measuring method of an integrated circuit, characterized in that. The method of claim 1, wherein step (b) (b1) dividing the pins of the integrated circuit into even and odd pins to model adjacent pins; (b2) opening a test equipment (PMU) connected to any one of the odd pins and even pins separated in step (b1) and applying 0 [V] through pin electronics (PE); (b3) opening the pin electronics (PE) and connecting the test equipment (PMU) to even or odd pins to which no voltage is applied through pin electronics in step (b2); And (b4) applying a pin of the test equipment (PMU) to the pin connected to the test equipment in step (b3) and applying a voltage to measure the voltage; How to measure. The method of claim 2, wherein step (b4) If the even and odd pins are short-circuited, the 0 [V] voltage applied to any one of the odd and even pins in step (b2) is measured, and a short circuit is determined. If the two pins are open, the test equipment ( PMU) A pin-to-pin defect measuring method for an integrated circuit, characterized in that a clamp voltage of 3 [V] is measured and determined to be good. The method of claim 1, wherein step (d) (d1) dividing the pins of the integrated circuit into even and odd pins to model the adjacent pins; (d2) Open the test equipment (PMU) connected to any one of the odd and even pins identified in step (d) and apply 5.0 [V] to each pin (or each pin) through pin electronics (PE). Applying 0.0 [V] to it; and (d3) When 5.0 [V] is applied to the even or odd pins which are not applied through pin electronics in step (d2) in step (d2), 0.0 [V] is used by using the test equipment (PMU). And applying 0.0 [V] using the test equipment PMU to measure leakage current when 0.0 [V] is applied in the step (d2). Method for measuring pin-to-pin defects in circuits. The method of claim 4, wherein step (d3) If there is a leakage resistance between the even and odd pins, the pin-to-pin leakage current IILpp is measured when 0.0 [V] is applied, and the pin-to-pin leakage current IIHpp is measured when 5.0 [V] is applied. IILpp or IIHpp is 0 [A] is measured because it is open between the pins.

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