JPH11295385A - Apparatus for verifying contact of electronic circuit element - Google Patents

Apparatus for verifying contact of electronic circuit element

Info

Publication number
JPH11295385A
JPH11295385A JP10102538A JP10253898A JPH11295385A JP H11295385 A JPH11295385 A JP H11295385A JP 10102538 A JP10102538 A JP 10102538A JP 10253898 A JP10253898 A JP 10253898A JP H11295385 A JPH11295385 A JP H11295385A
Authority
JP
Japan
Prior art keywords
electronic circuit
circuit element
contact
under test
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10102538A
Other languages
Japanese (ja)
Inventor
Shigeki Umeno
重貴 梅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP10102538A priority Critical patent/JPH11295385A/en
Publication of JPH11295385A publication Critical patent/JPH11295385A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain an apparatus for verifying the contact of an electronic circuit element of an I, etc., so that it can prevent the electronic circuit element from being broken due to overcurrent breakdown, etc. SOLUTION: Prior to various characteristic tests of an electronic circuit element, characteristics of protection diodes formed in an IC 1 under test are observed to verify the contact of the IC 1 under test to a characteristic test jig or electronic circuit element socket and other input/output terminal pins 5 than a terminal pin of the IC 1 are fixed to the level of a GND terminal 6. The drop voltage level with a reverse current flowing to the terminal under test is observed to make it possible to detect a failure, due to short-circuiting between terminals of the electronic circuit element under test at the same time as the poor contact between the element under test and characteristic test jig or electronic circuit element socket. Thus it is possible to verify the existence of the short circuit at the same time as the contact verification.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えばIC等の電
子回路素子の特性試験において、電子回路素子内部に形
成される保護ダイオードの特性を観察することにより、
電子回路素子と試験装置との間の接触の確認を行なうた
めの電子回路素子の接触確認装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a characteristic test of an electronic circuit element such as an IC, for example, by observing the characteristic of a protection diode formed inside the electronic circuit element.
The present invention relates to an electronic circuit element contact confirmation device for confirming contact between an electronic circuit element and a test device.

【0002】[0002]

【従来の技術】従来、図1に示すような電子回路素子で
ある例えばIC等の特性試験において、被試験ICと試
験治具あるいはICソケットとの接触を確認することを
目的に接触確認試験である所謂コンタクト試験を行な
う。このコンタクト試験は、図4に示すように、被試験
ICの被観測ピンのみにコンタクト試験用回路を接続
し、逆電流を流したときの降下電圧レベルを観察するこ
とによって行なわれる。
2. Description of the Related Art Conventionally, in a characteristic test of an electronic circuit element such as an IC as shown in FIG. A so-called contact test is performed. This contact test is performed by connecting a contact test circuit only to the pin to be observed of the IC under test and observing the voltage drop when a reverse current flows, as shown in FIG.

【0003】被観測ピンと、試験治具あるいはICソケ
ットとが正常に接触されている場合には、降下電圧レベ
ルはIC内部で各ピン−GND間に形成される保護ダイ
オードの特性により、図3中(C)に示すように一定の
範囲内で安定する。逆に、非接触状態であれば、図3中
(A)のように、降下電圧レベルが極端に大きくなる。
この電圧レベルにより接触の良否判定を行ない、全被観
測ピンが正常に接触されているときは以降の特性試験を
続行する。仮に全被観測ピンの内の1ピンでも非接触状
態が存在するものについては、コンタクト試験だけで以
後の各種の特性試験を停止させるので、接触不良による
誤試験を未然に防止することができるものとしている。
When the pin to be observed and the test jig or the IC socket are in normal contact, the voltage drop level is determined by the characteristics of the protection diode formed between each pin and GND inside the IC, as shown in FIG. It stabilizes within a certain range as shown in FIG. Conversely, in the non-contact state, the voltage drop level becomes extremely large as shown in FIG.
The quality of the contact is determined based on the voltage level. When all the pins to be observed are normally contacted, the subsequent characteristic test is continued. If one of all the pins to be observed has a non-contact state, the subsequent various characteristic tests are stopped only by the contact test, so that erroneous tests due to poor contact can be prevented beforehand. And

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
コンタクト試験においては、被試験ICの被観測ピン間
にショートが存在する場合には、上記コンタクト試験で
の検出が困難であり、以降の特性試験を被観測ピン間の
ショート状態で行なうこととなり、正確な試験を行なう
ことが不可能となるばかりでなく、以後の各種の特性試
験を続行することにより過電流破壊等を起こしてしまう
危険性が存在する。
However, in the conventional contact test, if there is a short circuit between the pins to be observed of the IC under test, it is difficult to detect the short-circuit by the above-mentioned contact test. Is performed in the short-circuit state between the pins to be observed, and not only is it impossible to perform an accurate test, but also there is a danger that overcurrent destruction may occur due to continuing various characteristic tests. Exists.

【0005】本出願に係る発明の目的は、過電流破壊等
によるIC等の電子回路素子の破壊を未然に防止できる
ようにした電子回路素子の接触確認装置を提供すること
にある。
An object of the invention according to the present application is to provide an electronic circuit element contact confirmation device capable of preventing the destruction of an electronic circuit element such as an IC due to overcurrent destruction or the like.

【0006】[0006]

【課題を解決するための手段】本出願に係る発明の目的
を実現する構成としては、請求項1に記載のように、電
子回路素子の各種特性試験行なう以前において、被試験
素子内部に形成される保護ダイオード特性を観測するこ
とにより、被試験素子と、特性試験治具あるいは電子回
路素子ソケットとの接触の確認を行なうものであって、
前記被試験素子の被観測端子以外をGNDレベルに固定
したことを特徴とする。
As a configuration for realizing the object of the invention according to the present application, as described in claim 1, before performing various characteristic tests of an electronic circuit device, the device is formed inside a device under test. By observing the characteristics of the protective diode, the contact between the device under test and the characteristic test jig or electronic circuit device socket is confirmed.
A terminal other than the observed terminal of the device under test is fixed at a GND level.

【0007】上記した構成によれば、電子回路素子の特
性試験のための接触確認試験において、被観測端子に逆
電流を流して降下電圧レベルを観測することにより、被
試験素子と、特性試験治具あるいは電子回路素子ソケッ
トとの接触不良の検出と同時に被試験電子回路素子の端
子間のショートによる不良も検出可能となる。このよう
に、接触確認と同時にショートの有無を確認することが
可能であるため、端子間ショート状態である場合では以
降の特性試験を行なわないようにすることで過電流破壊
等による被試験素子の破壊を未然に防止することができ
る。
According to the above configuration, in the contact confirmation test for the characteristic test of the electronic circuit element, a reverse current is applied to the terminal to be observed and the voltage drop level is observed, so that the element to be tested and the characteristic test repair can be performed. At the same time as detecting a contact failure with the tool or the electronic circuit element socket, a defect due to a short circuit between terminals of the electronic circuit element under test can be detected. As described above, since it is possible to confirm the presence or absence of a short circuit at the same time as contact confirmation, in the case of a short circuit between the terminals, by not performing the subsequent characteristic test, the device under test due to overcurrent destruction or the like can be prevented. Destruction can be prevented beforehand.

【0008】[0008]

【発明の実施の形態】(第1の実施の形態)図1乃至図
3は本発明の実施の形態を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS. 1 to 3 show an embodiment of the present invention.

【0009】図2は被試験IC1と、試験治具あるいは
ICソケットとの接触を確認する接触確認装置におい
て、IC端子である端子ピン4,5,6間がショート状
態であるか否かの確認を可能とした試験回路図である。
FIG. 2 shows a contact confirmation device for confirming contact between the IC under test 1 and a test jig or an IC socket, and confirms whether or not terminal pins 4, 5, and 6, which are IC terminals, are in a short state. FIG. 4 is a test circuit diagram that enables

【0010】この被試験IC1の被観測端子ピン4以外
のその他の入出力端子ピン5をGND端子6と共にGN
Dレベルに固定し、被観測端子ピン4に電流印加装置3
により電圧計2を介して逆電流を流し、降下電圧を観測
する。この降下電圧レベルは、被試験IC1内部に形成
される端子ピン4−GND間の保護ダイオードの特性で
あり、降下電圧が図3中(C)のように一定範囲内であ
れば正常に接触されていることになる。
The input / output terminal pins 5 other than the observed terminal pin 4 of the IC under test 1 are connected to the GND terminal 6 together with the GND terminal 6.
It is fixed to the D level, and the current applying device 3 is connected to the observed terminal pin 4.
, A reverse current is passed through the voltmeter 2 and the voltage drop is observed. This drop voltage level is a characteristic of the protection diode between the terminal pin 4 and GND formed inside the IC 1 under test. If the drop voltage is within a certain range as shown in FIG. Will be.

【0011】一方、仮に非接触状態であれば、図3中
(A)のように、保護ダイオードの特性が出ず、降下電
圧が極端に大きな値となり、非接触による不良と判定さ
れる。また、端子ピン4,5,6間にショート状態があ
る場合も、保護ダイオード特性が現れず、降下電圧は図
3中(B)のように極端に小さな値となり、ショートに
よる不良と判定される。
On the other hand, if it is in a non-contact state, as shown in FIG. 3A, the characteristics of the protection diode do not appear, the voltage drop becomes extremely large, and it is determined that there is a defect due to the non-contact. Also, when there is a short-circuit state between the terminal pins 4, 5, and 6, the protection diode characteristic does not appear, and the voltage drop becomes extremely small as shown in FIG. .

【0012】図1に示すように、以上の接触確認試験を
被試験IC1のGND端子6を除く全端子ピン4,5に
ついて行ない、被接触またはショートによる不良共に検
出されなかったICについては以降のDC特性試験やA
C特性試験等の各種の特性試験を実施し、一方、非接触
もしくはショートによる不良が検出されたものについて
は特性試験を停止する。
As shown in FIG. 1, the above-described contact confirmation test is performed on all terminal pins 4 and 5 except for the GND terminal 6 of the IC 1 under test. DC characteristics test and A
Various characteristic tests, such as a C characteristic test, are performed. On the other hand, the characteristic test is stopped when a defect due to non-contact or short circuit is detected.

【0013】[0013]

【発明の効果】請求項1に係る発明によれば、電子回路
素子の特性試験のための接触確認試験において、被観測
端子に逆電流を流して降下電圧レベルを観測することに
より、被試験素子と、特性試験治具あるいは電子回路素
子ソケットとの接触不良の検出と同時に被試験電子回路
素子の端子間のショートによる不良も検出可能となる。
このように、接触確認と同時にショートの有無を確認す
ることが可能であるため、端子間ショート状態である場
合では以降の特性試験を行なわないようにすることで過
電流破壊等による被試験素子の破壊を未然に防止するこ
とができる。
According to the first aspect of the present invention, in the contact confirmation test for the characteristic test of the electronic circuit element, a reverse current is caused to flow through the terminal to be observed, and the voltage drop level is observed. This makes it possible to detect a contact failure with the characteristic test jig or the electronic circuit element socket, and at the same time, a defect due to a short circuit between the terminals of the electronic circuit element under test.
As described above, since it is possible to confirm the presence or absence of a short circuit at the same time as contact confirmation, in the case of a short circuit between the terminals, by not performing the subsequent characteristic test, the device under test due to overcurrent destruction or the like can be prevented. Destruction can be prevented beforehand.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本出願に係る発明の第1の実施の形態における
ICの特性試験のフローチャート
FIG. 1 is a flowchart of an IC characteristic test according to a first embodiment of the present invention;

【図2】本出願に係る発明の第1の実施の形態における
接触確認装置を示す構成図
FIG. 2 is a configuration diagram showing a contact confirmation device according to the first embodiment of the present invention;

【図3】本出願に係る発明の第1の実施の形態における
接触確認装置の保護ダイオード特性の判定基準を説明す
るグラフ図
FIG. 3 is a graph illustrating a criterion for determining a protection diode characteristic of the contact confirmation device according to the first embodiment of the present invention;

【図4】従来例における接触確認装置を示す構成図FIG. 4 is a configuration diagram showing a contact confirmation device in a conventional example.

【符号の説明】[Explanation of symbols]

1…被試験IC 2…電圧計 3…電流印加装置 4…被観測端子
ピン 5…その他の入出力端子ピン 6…GND端子
REFERENCE SIGNS LIST 1 IC under test 2 voltmeter 3 current applying device 4 terminal pin under observation 5 other input / output terminal pins 6 GND terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電子回路素子の各種特性試験行なう以前
において、被試験素子内部に形成される保護ダイオード
特性を観測することにより、被試験素子と、特性試験治
具あるいは電子回路素子ソケットとの接触の確認を行な
うものであって、前記被試験素子の被観測端子以外をG
NDレベルに固定したことを特徴とする電子回路素子の
接触確認装置。
1. Prior to conducting various characteristics tests of an electronic circuit element, the characteristics of a protection diode formed inside the element under test are observed to make contact between the element under test and a characteristic test jig or an electronic circuit element socket. And checking the terminals other than the observed terminal of the device under test with G
An electronic circuit element contact confirmation device fixed at an ND level.
JP10102538A 1998-04-14 1998-04-14 Apparatus for verifying contact of electronic circuit element Pending JPH11295385A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10102538A JPH11295385A (en) 1998-04-14 1998-04-14 Apparatus for verifying contact of electronic circuit element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10102538A JPH11295385A (en) 1998-04-14 1998-04-14 Apparatus for verifying contact of electronic circuit element

Publications (1)

Publication Number Publication Date
JPH11295385A true JPH11295385A (en) 1999-10-29

Family

ID=14330057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10102538A Pending JPH11295385A (en) 1998-04-14 1998-04-14 Apparatus for verifying contact of electronic circuit element

Country Status (1)

Country Link
JP (1) JPH11295385A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100622071B1 (en) 2004-06-15 2006-09-08 박용수 A measuring method for pin-to-pin defect of IC
CN100335910C (en) * 2001-12-31 2007-09-05 技嘉科技股份有限公司 Open circuit/short circuit detector and its detection method
CN100432685C (en) * 2003-12-22 2008-11-12 威宇科技测试封装有限公司 Chip pin open circuit and short circuit tester and method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100335910C (en) * 2001-12-31 2007-09-05 技嘉科技股份有限公司 Open circuit/short circuit detector and its detection method
CN100432685C (en) * 2003-12-22 2008-11-12 威宇科技测试封装有限公司 Chip pin open circuit and short circuit tester and method therefor
KR100622071B1 (en) 2004-06-15 2006-09-08 박용수 A measuring method for pin-to-pin defect of IC

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