KR950009410B1 - Automatic recovery device of synchronous beffer - Google Patents

Abstract

The buffer of a synchronous transmission system is reconfigurated to the normal state by a hardware so that load of a CPU is minimized. The apparatus includes a buffer initializer(100) for setting an initial valid area of a buffer, a clock signal generator(300) for generating an over-head bit of a frame periodically according to frame signals and system clock signals, and a reset signal generator(800) for generating a reset control signal and a buffer overflow signal.

Description

Synchronous buffer automatic recovery device

1 is a block diagram of a synchronization buffer automatic recovery device according to the present invention.

Figure 2 is a detailed view of the buffer monitoring and reset signal generation control unit according to the present invention.

3 is a signal timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

100: buffer initialization unit 200: frame forming unit

300: clock forming unit 400: reset device

500: Synchronization buffer 600: Write address generator

700: read address generator

800: buffer monitoring and reset signal generation control unit

810: information region comparison unit 820: over header area comparison unit

830: comparison controller 840: buffer overrun / underrun monitoring unit

841 Accumulator 842 Periodic Accumulator

843: comparison unit

The present invention uses a signal generated by continuously detecting under-run / over-run of a mapping / historical buffer used in a low-speed multi-processing unit applied to a synchronous multiplexer of a synchronous transmission system during service. The present invention relates to a synchronous buffer recovery device that performs a buffer operation normally by newly generating a read / write address of itself without hardware.

In the prior art, hardware automatic buffer recovery is not possible. Therefore, in order to recover the buffer, power reset is performed manually or the abnormal state of the buffer is detected by the monitoring of the CPU to operate normally by the intervention of the process board. In synchronous transmitters, the amount of work to be done is excessive, and in a temporary situation such as a shaking of the clock, other functions may also cause a complex failure, causing a temporary congestion of various factors such as a domino phenomenon. In the apparatus having a problem that a situation that can not satisfy the automatic recovery time of the basic CCITT occurs.

In order to solve the above problems, the present invention reduces the load of the software CPU when a situation in which the clock is temporarily shaken due to an abnormal state or a circuit change in the device and an automatic recovery time cannot be satisfied occurs. An object of the present invention is to provide an automatic synchronization buffer recovery device for hardware recovery of a real-time buffer to a normal state.

In order to achieve the above object, the present invention provides a buffer initialization means for inputting a frame reference signal and a frame forming signal, receiving a system clock, and receiving a regular clock signal to control initial area setting and start of monitoring of the buffer, based on the frame reference. A frame forming means for receiving a signal and a system clock to form a C32 frame and providing the buffer address initialization means, a frame forming signal from the frame forming means, and a system clock to receive an overhead portion bit when forming a frame. Periodic clock forming means periodically generated on a frame and provided to the buffer address initialization unit, reset means for resetting address generation according to an automatic reset control signal, and frame write signal input and write / read address signals through the buffer address initialization means. Get input , Buffer monitoring and reset signal generation control to monitor the buffer automatically by receiving the automatic reset prevention signal and the 20m second signal and generate the automatic reset control signal according to the reset means and output the buffer overflow generation signal to the outside. Means for generating a write address by receiving an output signal and a system clock from the buffer initialization means and generating a read address by receiving an output signal and a system clock from the buffer initialization means. And a synchronous buffering means for receiving a write / read address signal from the write address generating means and the read address generating means, receiving data from the outside, storing the same, and outputting the data.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a block diagram of a synchronization buffer equipped with an automatic recovery device according to the present invention, in which 100 is a buffer initialization unit, 200 is a frame forming unit, 300 is a clock forming unit, 400 is a reset unit, 500 is a synchronization buffer, and 600. Denotes a write address generator, 700 denotes a read address generator, and 800 denotes a buffer monitoring and reset signal generation controller.

As shown in the figure, a buffer initialization unit 100 for inputting a frame reference signal and a frame forming signal, receiving a system clock, and receiving a regular clock forming signal to control the initial area setting of the buffer and the start of monitoring, the frame A frame forming unit 200 and a frame forming signal from the frame forming unit 200 are provided to the buffer address initialization unit 100 by forming a C32 frame by receiving a reference signal and a system clock. Periodic clock forming unit 300 to generate the overhead portion bits in the frame and receive the buffer address initialization unit 100 at the time of input frame formation, the reset unit 400 to reset the actual address generation to the value "0" (400). ), The frame forming signal is input through the buffer address initialization unit 100, and the write / read address signal is input, and the automatic reset method is performed. A buffer monitoring and reset signal generation control unit for receiving a signal and a 20m second signal and automatically monitoring a buffer and generating an automatic reset control signal accordingly to the reset unit 400 and outputting a buffer overflow generation signal to the outside. 800, a write address generator 600 for generating a write address by receiving an output signal and a system clock from the buffer initialization unit 100, and outputting an output signal and a system clock from the buffer initialization unit 100. It receives a read / write address signal from the read address generator 700, the write address generator 600, and the read address generator 700 to generate a read address, and receives and stores data from the outside. It consists of a synchronization buffer 500 for outputting data.

2 is a detailed view of a buffer monitoring and reset signal generation control unit according to the present invention, in which 810 is an information area comparison unit, 820 is an overhead header area comparison unit, 830 is a comparison control unit, 840 is a buffer overrun / underrun monitoring unit, 841 denotes an accumulator, 842 denotes a periodic accumulator, and 843 denotes a comparator.

As shown in the drawing, the comparison monitoring and reset signal generation controller receives a read / write address signal from the read / write address generators 700 and 600 of FIG. A read / write address from the read / write address generators 700 and 600 of FIG. An overhead header comparator that receives a signal and compares writing and reading in a portion where an overhead signal on a C32 frame is filled, transmits and receives a mutual comparison signal with the information area comparator 810, and outputs an overhead area comparison signal ( 820), the frame forming signal is inputted through the buffer address initialization unit 100 of FIG. 1, and the image area comparison signal from the information area comparison unit 810 is matched with the frame formation signal. A comparison control unit 830 for receiving an output signal from the header area comparison unit 820 and generating an information portion, an overhead portion, and an automatic reset signal, and a comparison control signal from the comparison control unit 830. Receives a buffer overrun / underrun monitoring unit 840 to monitor the buffer write twice (UNDERFLOW) / 2 reads (OVERFLOW) every 20m cycles and outputs a buffer overflow occurrence signal, the overrun / underrun monitoring unit 840 ), When comparing underrun / overrun of buffer, 1-5 out of 6 bits are compared with the same value in comparator. If the same value exists, pulse signal is generated from normal "zero" to "one" state. The number of underrun / overrun pulses applied by the application pulse p is accumulated in the accumulator 841 and the signals latched in the periodic accumulator 842 every 20m seconds signal n are buffer underrun / overrun even if only one occurrence occurs. To generate a signal (k) It is delivered to the interrupt processing module of the processor. If it is not generated even once in 20m seconds through the comparator 843, a release signal is generated, and the buffer overflow occurrence signal is "one" when the release signal is generated. When it is turned off and becomes "zero", the signal can be detected to detect normal and amorphous phases.

In more detail, the buffer monitoring and reset signal generation control unit 800 performs an address comparison generated by the C32 signal mapping / historical buffer read / write address comparator according to the present invention to automatically reset the comparison control unit 830. By sending the automatic reset control signal c to the reset device 400 under the control of the automatic reset prevention signal o, the address signals of the write address generator 600 and the weather address generator 700 are controlled. Becomes "0" as when a reset is engaged. At this time, even if any data i is received as the synchronization buffer, the write and read address signals are not operated until the frame reference signal b is applied. When the frame reference signal b for notifying the initial start is applied, the initial values d and e for which the forbidden band is set are applied from the buffer address initialization unit 100 to the write address generator 600 and the read address generator 700. The control signals of the write address generator 600 and the read area comparator generator 700 are the same as the data input i with the write address g and the read address h to be applied to the sync buffer 500. The phase is applied to the synchronization buffer 500 to prevent slippage of data. At this time, the write address (g) and the read address (h) is operated by setting a prohibition band in which the address of the two signals maintains a constant interval.

This constant forbidden band always operates as a constant forbidden band unless there is a clock shake or other circuit malfunction in the frame forming unit 200 and the regular signal forming unit 300. Since the number of system clocks of information bits on the C32 frame and the number of clocks of the regular clock forming unit 300 are the same, the write address (g) and read address (h) signals are signals indicating the address of the buffer. The value changes only at the bit position.

The control signal generated by the rule clock forming unit 300 changes the value of the overhead area with regularity in the entire area of the C32 frame.

The output signals of the write address generator 600 and the read address generator 700 are applied to the buffer monitoring and reset signal generation control unit 800 to monitor continuously during service. The address signal which is an input signal of the buffer monitoring and reset signal generation control unit 800 is a 6-bit parallel signal in binary. The LSB is represented by 2 bits on the sync buffer, and the upper right of the LSB has 4 bits of margin. The binary value of 6 bits represents the address to write and read the data value on the sync buffer. Compare with write and read addresses, respectively, and when the same value occurs, it occurs in the underrun / overrun 2-bit area of the buffer and data can be dropped.

Therefore, the underrun / overrun of the buffer in the comparison between the information area comparator 810 and the overhead area comparator 820 is to compare whether the binary values of 1 to 5 of the 6 bits are the same in the comparator. If the same value exists, the pulser signal is generated from the normal "zero" state to the "one" state and is applied from the comparison controller 830 to the buffer overrun / underrun monitoring unit 840. The number of underrun / overrun pulses applied with this applied pulse p is accumulated in the accumulator 841, and the signal latched to the periodic cumulative sphere 842 every 20m seconds corals n is buffer underrun / The overrun signal k is generated and transmitted to the interrupt processing module of the processor. If not even once in 20m seconds, a release signal is generated. The buffer underrun / overrun (k) signal becomes a binary signal "one" when generated and "zero" when released. Normal and abnormal can be detected by detecting this signal.

The automatic reset control signal c of the comparison control unit 830 is enabled / disabled by the automatic reset prevention signal o signal, and real time automatic recovery is performed only when the automatic reset control signal c is enabled.

3 is a signal timing diagram according to the present invention, (A) is a C32 frame configuration diagram, (B) is a frame formation structure diagram when address count high, and (C) is a regular clock formation diagram when address count high (D) shows an automatic reset control signal timing diagram, (E) shows a buffer overrun / underrun signal structure diagram and a timing diagram, respectively.

Each explanation is as follows.

POH is an overhead part for communication of messages with other transmitters when the transmitter is composed of one network element, R is a part where information is fixedly filled with "0" or "1" and C bit Is a Stirling control signal indicating whether to stuff at the S position.

The part marked "0" is a reserved bit for future data communication. The portion where the pure DS3 signal is inserted is indicated by 1, and the total amount of information of 696 bits is inserted in one subframe. Of the 696 bits of information, 622 (1) is a bit for transmitting information, and 75 (4) is an overhead part for data communication of the device. Regular subtraction of the 75 (4) bits on the subframe is the regular clock forming unit structure of (C), and the frame forming unit of (B) is a signal indicating the 1-bit part where pure information is transmitted when it is high as "1". .

Referring to the automatic recovery by the automatic reset control signal of (D), when the control signals of the signal lines g and h of the first and second signals inform the same address, a pulse of c is generated and the buffer is reset to f and It will be in the same state. This signal is initialized again when the frame signal of b is generated, and the corresponding address is initialized to the prohibited area, and the buffer is in a normal state.

Even in such a situation, when a failure occurs again and an overlap of addresses occurs, the above form is repeated.

In (E), the report of the fault to the monitoring unit signals a collision of addresses within 20m seconds, and when the collision occurs, the same data is continuously read. Therefore, the state of the information becomes an error state. In (E), two collisions occur during the first 20m seconds of n, resulting in a fault condition of "1".

In 20m seconds, when the collision signal p never occurs, the transition occurs to the normal state "0" indicating the release.

As described above, the present invention reduces CPU overload and automatically recovers the hardware, and automatically recovers the result of the service unavailability. Thus, the time required is performed in real time due to hardware processing.

Claims (2)

A buffer initialization means 100 for inputting a frame reference signal and a frame forming signal, receiving a system clock, receiving a regular clock forming signal, and controlling an initial region setting and monitoring start of a buffer, and inputting the frame reference signal and the system clock. Receiving a frame forming signal from the frame forming means 200 and the frame forming means 200 and providing a system clock to the buffer address initialization means 100, and receiving a system clock. Periodic clock forming means (300) for generating partial bits periodically on the frame and providing them to the buffer address initialization unit (100), Reset means (400) for resetting address generation according to an automatic reset control signal, and the buffer address initialization means The frame forming signal is input through the 100 and the write / read address signal is input, and Automatically monitors the buffer by receiving the reset prevention signal and the 20m second signal, and generates the automatic reset control signal accordingly to the reset means 400 and outputs the buffer overflow generation signal to the outside. A control address 800, an output signal from the buffer initialization means 100, a write address generation means 600 for generating a write address by receiving a system clock, and an output signal from the buffer initialization means 100; Read address generating means 700 for receiving a system clock and generating a read address, and write / read address signals are input from the write address generating means 600 and read address generating means 700 to receive data from the outside. Synchronous buffer automatic recovery device characterized in that it comprises a synchronous buffering means 500 for receiving and storing and outputting data. . The method of claim 1, wherein the buffer monitoring and reset signal generation control means (800); The read / write address generator 700, 600 receives a read / write address signal and receives an over header area comparison signal to compare the write and read in the portion where the information signal on the C32 frame is filled, thereby comparing the information area comparison signal. A read / write address signal is input from the information area comparator 810 and the read / write address generating means 700 and 600, and the write and read are compared at a portion where the overhead signal on the C32 frame is filled. Receiving a frame forming signal through the header area comparison means 820 and the buffer address initialization means 100 for transmitting and receiving a mutual comparison signal with the information area comparison unit 810 and outputting an overhead area comparison signal. Receives an output signal from the area comparison means 810 and an output signal from the overheader area comparison means 820 and overwrites the information portion. The second control unit 830 and the second control unit UNDFLOW / 2 reads (OVERFLOW) of the buffer every 20m in response to the comparison control unit 830 and the comparison control unit 830 generating the automatic reset signal. And automatic buffer overrun / underrun monitoring means (840) for monitoring and outputting a buffer overflow occurrence signal.