KR950010428A - Synchronous buffer automatic recovery device - Google Patents

Abstract

The present invention utilizes a signal generated by continuously detecting under-run / over-run of a mapping / historical buffer used in a low-speed multiprocessor applied to a synchronous multiplexer of a synchronous transmission system during service. It is a synchronous buffer recovery device that performs a buffer operation normally by newly creating its own read / write address in hardware without the help of software. It reduces CPU overload and recovers automatically by the hardware itself. In addition, since the service result is automatically recovered as a result of the check of the service unavailable state, the time required is performed in real time due to hardware processing.

Description

Synchronous buffer automatic recovery device

Since this is an open matter, no full text was included.

1 is a block diagram of a synchronization buffer automatic recovery device according to the present invention.

Figure 2 is a detailed view of the buffer monitoring and reset signal generation control unit according to the present invention.

3 is a signal timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

100: buffer initialization unit 200: frame forming unit

300: clock forming unit 400: reset device

500: Synchronization buffer 600: Write address generator

700: read address generator

800: buffer monitoring and reset signal generation control unit

810: information region comparison unit 820: over header area comparison unit

830: comparison controller 840: buffer overrun / underrun monitoring unit

841 Accumulator 842 Periodic Accumulator

843: comparison unit

Claims (2)

A buffer initialization means 100 for inputting a frame reference signal and a frame forming signal, receiving a system clock, receiving a regular clock forming signal, and controlling an initial region setting and monitoring start of a buffer, and inputting the frame reference signal and the system clock. Receiving a frame forming signal from the frame forming means 200 and the frame forming means 200 and providing a system clock to the buffer address initialization means 100, and receiving a system clock. Periodic clock forming means (300) for generating partial bits periodically on the frame and providing them to the buffer address initialization unit (100), Reset means (400) for resetting address generation according to an automatic reset control signal, and the buffer address initialization means The frame forming signal is input through the 100 and the write / read address signal is input, and Automatically monitors the buffer by receiving the reset prevention signal and the 20m second signal, and generates the automatic reset control signal accordingly to the reset means 400 and outputs the buffer overflow generation signal to the outside. A control address 800, an output signal from the buffer initialization means 100, a write address generation means 600 for generating a write address by receiving a system clock, and an output signal from the buffer initialization means 100; Read address generating means 700 for receiving a system clock and generating a read address, and write / read address signals are input from the write address generating means 600 and read address generating means 700 to receive data from the outside. Synchronous buffer automatic recovery device characterized in that it comprises a synchronous buffering means 500 for receiving and storing and outputting data. . The method of claim 1, wherein the buffer monitoring and reset signal generation control means (800); The read / write address signal is input from the read / write address generating means (700, 600) and the over header area comparison signal is input to compare the write and read at the portion where the information signal on the C32 frame is filled. Read and write address signals are input from the information area comparison means 810 and the read / write address generating means 700 and 600, and the write and read comparison is performed at a portion where an overhead signal on a C32 frame is filled. Receiving a frame forming signal through the header area comparison means 820 and the buffer address initialization means 100 for transmitting and receiving a mutual comparison signal with the information area comparison unit 810 and outputting an overhead area comparison signal. The output signal from the area comparison means 810 and the output signal from the overheader area comparison means 810 and the overheader area comparison The control unit 830 receives the output signal from the stage 820 and generates the information portion, the overhead portion, and the automatic reset signal, and receives the comparison control signal from the comparison control means 830 in a period of 20 m. And a buffer overrun / underrun monitoring means (840) for monitoring a buffer overflow occurrence signal by monitoring write twice (UNDERFLOW) / 2 reads (OVERFLOW) of the buffer. ※ Note: The disclosure is based on the initial application.