KR970031520A

KR970031520A - A display device of address and data of I ^ 2 ^ C protocol bus

Info

Publication number: KR970031520A
Application number: KR1019950041355A
Authority: KR
Inventors: 김정섭
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1995-11-14
Filing date: 1995-11-14
Publication date: 1997-06-26

Abstract

본 발명은 I²C 프로토콜 버스로 전송되는 어드레스와 데이터를 시각적으로 확인할 수 있게 하는 I²C 프로토콜 버스의 어드레스와 데이터의 디스플레이 장치에 관한 것으로서, 본 발명은 I²C 프로토콜 버스로 전송되는 '시작' 비트와 '종료' 비트 사이의 어드레스와 데이터를 일시 저장한 후 디스플레이 디바이스를 통해 디스플레이함으로 어드레스 및 데이터가 제대로 전송되는 지를 시각적으로 확인하고 감시할 수 있게 되는 효과가 있는 것이다.The present invention relates to a display device, the address and the data on the I ² C protocol bus to allow visualization of the address and the data sent to the I ² C protocol, the bus, the present invention is started, it is sent to the I ² C protocol bus By temporarily storing the address and data between the 'bit' and 'end' bits and displaying them through the display device, it is possible to visually check and monitor whether the address and data are properly transmitted.

Description

A display device of address and data of I2C protocol bus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 I²C프로토콜 버스의 어드레스와 데이터의 디스플레이 장치의 구성도.3 is a block diagram of an apparatus for displaying address and data of an I ² C protocol bus according to the present invention.

제4도는 본 발명의 시작/종료 비트 인식부의 구성도이다.4 is a block diagram of the start / end bit recognition unit of the present invention.

Claims

A start / end bit recognition unit 11 for receiving a sync clock of the SCL bus and an address and data of the SDA bus to recognize a 'start' bit and a 'end'bit; A control unit 12 receiving an output signal of the start / end bit recognition unit 11; A counter (13) driven by the control of the controller (12) to count the synchronous clock of the SCL bus and output an OUT signal to the controller (12); A shift register 15 for receiving and storing a synchronization clock of the SCL bus and an address and data of the SDA bus; A first latch unit 16 temporarily storing data stored in the shift register 15 under the control of the control unit 12; A second latch unit 17 which temporarily stores an address stored in the shift register 15 under the control of the control unit 12; First display means for displaying data stored in the first latch portion 16; The second latch section 17, the second I ² C protocol, the display unit of the address and data bus, characterized in that consists of a display means for displaying the address stored in the.

The method of claim 1, further comprising a reception response bit output unit 14 for detecting an OUT signal output from the counter 13 to the control unit 12 and outputting a reception response (ACK) signal to the transmission side. A device for displaying an address and data of an I ² C protocol bus.

2. The apparatus of claim 1, wherein the start / end bit recognition unit (1l) comprises: a first D-flip flop (24) for receiving a synchronization clock of an SCL bus and an address and data of an SDA bus; A second D-flip flop 25 which receives the inverted synchronous clock of the SCL bus and the address and data of the SDA bus and outputs an output signal to the controller 12; Exclusive OR gate 26 which receives the output signal of the first D-flip flop 24 and the output signal of the second D-flip flop 25, performs an exclusive OR, and outputs the result to the controller 12. Device for displaying the address and data of an I ² C protocol bus.

※ Note: The disclosure is based on the initial application.